AM29LV800DB120EC SPANSION [SPANSION], AM29LV800DB120EC Datasheet

Page 1

Am29LV800D Data Sheet This product has been retired and is not recommended for designs. For new and current designs, S29AL008D supersedes Am29LV800D and is the factory-recommended migration path for this device. Please refer to the S29AL008D data sheet for specifications ...

Page 2

THIS PAGE LEFT INTENTIONALLY BLANK. ...

Page 3

DATA SHEET Am29LV800D 8 Megabit ( 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory This product has been retired and is not recommended for designs. For new and current designs, S29AL008D supersedes Am29LV800D and is ...

Page 4

GENERAL DESCRIPTION The Am29LV800D Mbit, 3.0 volt-only Flash memory organized as 1,048,576 bytes or 524,288 words. The device is offered in 48-ball FBGA, 44-pin SO, and 48-pin TSOP packages. For more informa ...

Page 5

TABLE OF CONTENTS Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4 Block Diagram . . . . . . . . . . ...

Page 6

PRODUCT SELECTOR GUIDE Family Part Number Speed Options Full Voltage Range: V Max access time ACC Max CE# access time Max OE# access time Note: See “AC Characteristics” for ...

Page 7

CONNECTION DIAGRAMS A15 1 A14 2 A13 3 A12 4 A11 5 6 A10 WE# 11 RESET RY/BY# 15 A18 16 A17 ...

Page 8

CONNECTION DIAGRAMS A6 B6 A13 A12 WE# RESET RY/BY A17 Special Handling Instructions for FBGA Package Special handling is required for Flash Memory prod- ...

Page 9

PIN CONFIGURATION A0–A18 = 19 addresses DQ0–DQ14 = 15 data inputs/outputs DQ15/A-1 = DQ15 (data input/output, word mode), A-1 (LSB address input, byte mode) BYTE# = Selects 8-bit or 16-bit mode CE# = Chip enable OE# = Output enable WE# ...

Page 10

ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combi- nation) is formed by a combination of the elements below. Am29LV800D T - DEVICE NUMBER/DESCRIPTION Am29LV800D 8 Megabit ...

Page 11

DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory loca- tion. The register is composed of ...

Page 12

Writing Commands/Command Sequences To write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive WE# and CE and OE ...

Page 13

If RESET# is asserted during a program or erase op- eration, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of t (during Embedded Algorithms). The sys- READY tem can thus ...

Page 14

Table 3. Am29LV800DB Bottom Boot Block Sector Addresses Sector A18 A17 A16 A15 SA0 SA1 SA2 SA3 SA4 SA5 0 ...

Page 15

Table 4. Am29LV800D Autoselect Codes (High Voltage Method) Description Mode CE# Manufacturer ID: AMD L Device ID: Word L Am29LV800B Byte L (Top Boot Block) Device ID: Word L Am29LV800B Byte L (Bottom Boot Block) Sector Protection Verification L Legend: ...

Page 16

START PLSCNT = 1 RESET Wait First Write Temporary Sector Cycle = 60h? Unprotect Mode Yes Set up sector address Sector Protect: Write 60h to sector address with ...

Page 17

Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 5 for com- mand definitions). In addition, the following hardware data protection measures prevent accidental erasure or ...

Page 18

Table 5 shows the address and data require- ments. This method is an alternative to that shown in Table 4, which is intended for PROM programmers and requires V ...

Page 19

Write Program Command Sequence Data Poll from System Embedded Program algorithm in progress Verify Data? No Increment Address Last Address? Programming Completed Note: See Table 5 for program command sequence. Figure 3. Program Operation Chip Erase Command Sequence Chip erase ...

Page 20

Once the sector erase operation has begun, only the Erase Suspend command is valid. All other com- mands are ignored. Note that a hardware reset dur- ing the sector erase operation immediately terminates the operation. The Sector Erase command sequence ...

Page 21

Table 5. Am29LV800D Command Definitions Command Sequence (Note 1) Read (Note 6) 1 Reset (Note 7) 1 Word Manufacturer ID 4 Byte Word Device ID, 4 Top Boot Block Byte Word Device ID, 4 Bottom Boot Block Byte Word Sector ...

Page 22

WRITE OPERATION STATUS The device provides several bits to determine the sta- tus of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. Table 6 and the following subsections describe the functions of these bits. DQ7, RY/BY#, and DQ6 ...

Page 23

RY/BY#: Ready/Busy# The RY/BY dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since ...

Page 24

still toggling, the de- vice did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially ...

Page 25

Operation Embedded Program Algorithm Standard Mode Embedded Erase Algorithm Reading within Erase Suspended Sector Erase Suspend Reading within Non-Erase Mode Suspended Sector Erase-Suspend-Program Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the ...

Page 26

ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C Ambient Temperature with Power Applied ...

Page 27

DC CHARACTERISTICS CMOS Compatible Parameter Description I Input Load Current Input Load Current LIT I Output Leakage Current LO V Active Read Current CC I CC1 (Notes Active Write Current CC I CC2 (Notes ...

Page 28

DC CHARACTERISTICS (Continued) Zero Power Flash 500 1000 Note: Addresses are switching at 1 MHz Figure 9. I Current vs. Time (Showing Active and Automatic Sleep Currents) CC1 ...

Page 29

TEST CONDITIONS Device Under Test C 6.2 kΩ L Note: Diodes are IN3064 or equivalent Figure 11. Test Setup KEY TO SWITCHING WAVEFORMS WAVEFORM Don’t Care, Any Change Permitted 3.0 V 1.5 V Input 0.0 V Am29LV800D_00_A7 December 4, 2006 ...

Page 30

AC CHARACTERISTICS Read Operations Parameter JEDEC Std t t Read Cycle Time (Note 1) AVAV Address to Output Delay AVQV ACC t t Chip Enable to Output Delay ELQV Output Enable to Output Delay ...

Page 31

AC CHARACTERISTICS Hardware Reset (RESET#) Parameter JEDEC Std Description RESET# Pin Low (During Embedded t READY Algorithms) to Read or Write (See Note) RESET# Pin Low (NOT During Embedded t READY Algorithms) to Read or Write (See Note) t RESET# ...

Page 32

AC CHARACTERISTICS Word/Byte Configuration (BYTE#) Parameter JEDEC Std t t CE# to BYTE# Switching Low or High ELFL/ ELFH t BYTE# Switching Low to Output HIGH Z FLQZ t BYTE# Switching High to Output Active FHQV CE# OE# BYTE# BYTE# ...

Page 33

AC CHARACTERISTICS Erase/Program Operations Parameter JEDEC Std t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL Address Hold Time WLAX Data Setup Time DVWH Data ...

Page 34

AC CHARACTERISTICS Program Command Sequence (last two cycles Addresses 555h CE Data RY/BY VCS Notes program address program data Illustration ...

Page 35

AC CHARACTERISTICS Erase Command Sequence (last two cycles Addresses 2AAh CE Data 55h RY/BY# t VCS V CC Notes sector address (for Sector Erase Valid ...

Page 36

AC CHARACTERISTICS t RC Addresses VA t ACC OE# t OEH WE# DQ7 DQ0–DQ6 t BUSY RY/BY# Note Valid address. Illustration shows first status cycle after command sequence, last status read ...

Page 37

AC CHARACTERISTICS Enter Erase Embedded Suspend Erasing Erase Erase Suspend WE# DQ6 DQ2 Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an erase-suspended sector. Temporary Sector ...

Page 38

AC CHARACTERISTICS RESET# SA, A6, A1, A0 Sector Protect/Unprotect Data 60h 1 µs CE# WE# OE# * For sector protect For sector unprotect ...

Page 39

AC CHARACTERISTICS Alternate CE# Controlled Erase/Program Operations Parameter JEDEC Std t t Write Cycle Time (Note 1) AVAV Address Setup Time AVEL Address Hold Time ELAX Data Setup Time DVEH DS ...

Page 40

AC CHARACTERISTICS 555 for program 2AA for erase Addresses WE# OE# CE Data t RH RESET# RY/BY# Notes program address program data, DQ7# = complement of the data written ...

Page 41

ERASE AND PROGRAMMING PERFORMANCE Parameter Sector Erase Time Chip Erase Time Byte Programming Time Word Programming Time Byte Mode Chip Programming Time (Note 3) Word Mode Notes: 1. Typical program and erase times assume the following conditions: 25 programming typicals ...

Page 42

PHYSICAL DIMENSIONS* TS 048—48-Pin Standard TSOP * For reference only. BSC is an ANSI standard for Basic Space Centering Am29LV800D Am29LV800D_00_A7 December 4, 2006 Dwg rev AA; 10/99 ...

Page 43

PHYSICAL DIMENSIONS FBB 048—48-Ball Fine-Pitch Ball Grid Array (FBGA Am29LV800D_00_A7 December 4, 2006 Am29LV800D Dwg rev AF; 10/99 41 ...

Page 44

PHYSICAL DIMENSIONS VBK 048 - 48 Ball Fine-Pitch Ball Grid Array (FBGA) 6. INDEX MARK PIN A1 CORNER 10 TOP VIEW A SEATING PLANE A1 SIDE VIEW PACKAGE VBK 048 JEDEC N/A 6. 8.15 ...

Page 45

PHYSICAL DIMENSIONS SO 044—44-Pin Small Outline Package Am29LV800D_00_A7 December 4, 2006 Am29LV800D Dwg rev AC; 10/99 43 ...

Page 46

REVISION SUMMARY Revision A (January 19, 2004) Changed data sheet status to Advance Information to indicate new 0.23 µm process technology. The base device part number has changed from Am29LV800B to Am29LV800D. Specifications for I t have changed. Extended temperature ...