AM29PDL128G AMD [Advanced Micro Devices], AM29PDL128G Datasheet
AM29PDL128G
Related parts for AM29PDL128G
AM29PDL128G Summary of contents
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Data Sheet July 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig- inally developed the specification, these ...
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THIS PAGE LEFT INTENTIONALLY BLANK. 2 October 13, 2004 ...
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... Am29PDL128G 128 Megabit ( 16-Bit 32-Bit) CMOS 3.0 Volt-only, Simultaneous Read/ Write Flash Memory with VersatileIO DISTINCTIVE CHARACTERISTICS ARCHITECTURAL ADVANTAGES 128Mbit Page Mode device — Word (16-bit) or double word (32-bit) mode selectable via WORD# input — Page size of 8 words/4 double words: Fast page read access ...
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... GENERAL DESCRIPTION The Am29PDL128G is a 128 Mbit, 3.0 volt-only Page Mode and Simultaneous Read/Write Flash memory device orga- nized as 8 Mwords double words (One word is equal to two bytes). The device is offered in an 80-ball Fortified BGA package. The word-wide data (x16) appears on DQ15-DQ0 ...
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... Simultaneous Read/Write Block Diagram . . . . . . 7 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 8 Pin Description Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Ordering Information . . . . . . . . . . . . . . . . . . . . . . 10 Device Bus Operations . . . . . . . . . . . . . . . . . . . . 11 Table 1. Am29PDL128G Device Bus Operations ...........................11 Word/Double Word Configuration........................................... 11 Requirements for Reading Array Data ................................... 11 Random Read (Non-Page Read) ........................................... 11 Page Mode Read .................................................................... 12 Table 2. Page Select, Double Word Mode ......................................12 Table 3 ...
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... Unprotect Timing Diagram ............................................................. 63 Alternate CE# Controlled Erase and Program Operations ..... 64 Figure 26. Alternate CE# Controlled Write (Erase/Program) Operation Timings.......................................................................... 65 Erase And Programming Performance Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 66 BGA Ball Capacitance . . . . . . . . . . . . . . . . . . . . . 66 Data Retention Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 67 LAB080—80-Ball Fortified Ball Grid Array package .............................................................. 67 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 68 Am29PDL128G 5 ...
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... Sector Switches Erase Voltage Generator PGM Voltage Generator Chip Enable Output Enable Logic A3, A4 Y-Decoder STB Timer X-Decoder Am29PDL128G Am29PDL128G DQ31–DQ0 V IO Input/Output Buffers STB Data Latch Y-Gating Cell Matrix October 28, 2004 ...
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... STATE WE# CONTROL CE# & DW/W# COMMAND WP# REGISTER ACC DQ0–DQ15 A21–A0 Mux October 28, 2004 OE# DW/W# Bank 1 Bank 1 Address X-Decoder Bank 2 Address Bank 2 X-Decoder Status Control X-Decoder Bank 3 Bank 3 Address X-Decoder Bank 4 Address Bank 4 Am29PDL128G DQ31–DQ0 Mux 7 ...
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... DQ20 DQ22 DQ3 DQ21 DQ6 DQ2 DQ19 DQ5 V IO integrity may be compromised if the package body is exposed to temperatures above 150 periods of time. Am29PDL128G DQ9 V A18 DQ24 A19 A17 DQ8 A16 A15 A14 ...
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... V = Output Buffer Power Supply Device Ground Pin Not Connected Internally RFU = Reserved for Future Use October 28, 2004 LOGIC SYMBOL 22 A21–A0 CE# OE# WE# WP# ACC RESET# WORD Am29PDL128G DQ31–DQ0 (A-1) RY/BY# 9 ...
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... PE = 80-Ball Fortified Ball Grid Array ( 1 mm pitch package (LAB080) SPEED OPTION See Product Selector Guide and Valid Combinations Valid Combinations for BGA Packages Order Number Am29PDL128G70R Am29PDL128G70 Am29PDL128G80 Am29PDL128G90 Am29PDL128G ° BGA) Package Marking PD128G70R PEF I,F PEI PD128G70V ...
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... The command register itself does not occupy any addressable memory loca- tion. The register is a latch used to store the com- mands, along with the address and data information needed to execute the command. The contents of the Table 1. Am29PDL128G Device Bus Operations Operation CE# OE# Read ...
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... I in the 1 CC2 tive current specification for the write mode. See 0 Characteristics” bles and timing diagrams for write operations. 1 Am29PDL128G Table 4. Bank Select Bank A21–A19 Bank 1 000 Bank 2 001, 010, 011 Bank 3 100, 101, 110 Bank 4 111 , and OE ...
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... The system can read data t SET# pin returns to V Refer to tables in rameters and to Output Disable Mode When the OE# input disabled. The output pins (except for RY/BY#) are placed in the high impedance state. Am29PDL128G ACC DC Characteris- RP ±0.3 V, the device SS ±0.3 V, the standby cur- SS (during Embedded Algorithms) ...
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... C8000h–CFFFFh 32/16 D0000h–D7FFFh 32/16 D8000h–DFFFFh 32/16 E0000h–E7FFFh 32/16 E8000h–EFFFFh 32/16 F0000h–F7FFFh 32/16 F8000h–FFFFFh Am29PDL128G Address Range (x32) 000000h–0007FFh 000800h–000FFFh 001000h–0017FFh 001800h–001FFFh 002000h–0027FFh 002800h–002FFFh 003000h–0037FFh 003800h–003FFFh 004000h–007FFFh 008000h–00BFFFh 00C000h–00FFFFh 010000h–013FFFh 014000h– ...
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... Am29PDL128G Address Range (x32) 080000h–083FFFh 084000h–087FFFh 088000h–08BFFFh 08C000h–08FFFFh 090000h–093FFFh 094000h–097FFFh 098000h–09BFFFh 09C000h–09FFFFh 0A0000h–0A3FFFh 0A4000h–0A7FFFh 0A8000h–0ABFFFh 0AC000h–0AFFFFh 0B0000h– ...
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... Am29PDL128G Address Range (x32) 128000h–12BFFFh 12C000h–12FFFFh 130000h–133FFFh 134000h–137FFFh 138000h–13BFFFh 13C000h–13FFFFh 140000h–143FFFh 144000h–147FFFh 148000h–14BFFFh 14C000h–14FFFFh 150000h–153FFFh 154000h–157FFFh 158000h– ...
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... A48000h–4BFFFFh Am29PDL128G Address Range (x32) 1C4000h–1C7FFFh 1C8000h–1CBFFFh 1CC000h–1CFFFFh 1D0000h–1D3FFFh 1D4000h–1D7FFFh 1D8000h–1DBFFFh 1DC000h–1DFFFFh 1E0000h–1E3FFFh 1E4000h–1E7FFFh 1E8000h–1EBFFFh 1EC000h–1EFFFFh 1F0000h–1F3FFFh 1F4000h– ...
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... Am29PDL128G Address Range (x32) 260000h–263FFFh 264000h–267FFFh 268000h–26BFFFh 26C000h–26FFFFh 270000h–273FFFh 274000h–277FFFh 278000h–27BFFFh 27C000h–27FFFFh 280000h–283FFFh 284000h–287FFFh 288000h–28BFFFh 28C000h–28FFFFh 290000h– ...
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... Am29PDL128G Address Range (x32) 2FC000h–2FFFFFh 300000h–303FFFh 304000h–307FFFh 308000h–30BFFFh 30C000h–30FFFFh 310000h–313FFFh 314000h–317FFFh 318000h–31BFFFh 31C000h–31FFFFh 320000h–323FFFh 324000h–327FFFh 328000h–32BFFFh 32C000h– ...
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... A21:A0 in double word mode (WORD#=V IL Am29PDL128G Address Range (x32) 380000h–383FFFh 384000h–387FFFh 388000h–38BFFFh 38C000h–38FFFFh 390000h–393FFFh 394000h–397FFFh 398000h–39BFFFh 39C000h–39FFFFh 3A0000h–3A3FFFh 3A4000h–3A7FFFh 3A8000h– ...
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... Bank Address Sector Address Don’t care. IH Am29PDL128G (x32) (x16) Address Range Address Range 000000h–00007Fh Table 14 and Table Table 16. This method . Refer to “Autoselect Command ID DQ31 to DQ8 DQ7 (Word/Double DQ0 Word) ...
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... Am29PDL128G A12 A11 Sectors 0 0 SA0 0 1 SA1 1 0 SA2 1 1 SA3 0 0 SA4 0 1 SA5 1 0 SA6 1 1 SA7 X X SA8 to SA10 X X SA11 to SA14 ...
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... Am29PDL128G A12 A11 Sectors X X SA103 to SA106 X X SA107 to SA110 X X SA111 to SA114 X X SA115 to SA118 X X SA119 to SA122 X X SA123 to SA126 X X SA127 to SA130 X X SA131 to SA134 ...
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... SGA79 SECTOR PROTECTION The Am29PDL128G features several levels of sector protection, which can disable both the program and erase operations in certain sectors or sector groups: Persistent Sector Protection A command sector protection method that replaces the old 12 V controlled protection method. Password Sector Protection ...
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... First, the PPB Lock bit must be dis- abled by either putting the device through a power-cy- cle, or hardware res et. The PPBs can then be changed to reflect the desired settings. Setting the PPB lock bit once again locks the PPBs, and the de- vice operates normally again. Am29PDL128G 25 ...
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... While programming in the password region, the customer may perform Password Verify operations. Once the desired password is programmed in, the customer must then set the Password Mode Locking Bit. This operation achieves two objectives: Am29PDL128G See “Utilizing Password on page 30 for more October 28, 2004 ...
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... The proce- dure requires high voltage (V RESET# pin. Refer to dure. Note: For sector unprotect, all unprotected sec- tors must first be protected prior to the first sector write cycle. Am29PDL128G “High Voltage Sector placed on the ID Table 1 for details on this proce- ...
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... Reset PLSCNT = 1 Increment PLSCNT No Yes PLSCNT = 1000? Yes Device failed Sector Unprotect Algorithm Am29PDL128G START PLSCNT = 1 RESET Wait 1 µs No First Write Temporary Sector Cycle = 60h? Unprotect Mode Yes No All sectors protected? Yes ...
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... If the security feature is not required, the SecSi Sector can be treated as an additional Flash memory space. The SecSi Sector can be read any number of times, but can be programmed and locked only once. Note: The accelerated programming (ACC) and unlock by- Am29PDL128G “Enter SecSi Sector/Exit on page 35). After 29 ...
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... In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during V power-up and power-down transitions, or from system noise. Am29PDL128G Step 2. Step 3. If data = 00h, SecSi Sector is ...
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... Primary OEM Command Set 0000h 0040h Address for Primary Extended Table 0000h 0000h Alternate OEM Command Set (00h = none exists) 0000h 0000h Address for Alternate OEM Extended Table (00h = none exists) 0000h Am29PDL128G 10, 11, 12, and 13. To terminate read- Tables 10, 11, 12, Description 31 ...
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... Typical timeout for full chip erase 2 0005h Max. timeout for byte/word write 2 0000h Max. timeout for buffer write 2 0004h Max. timeout per individual block erase 2 0000h Max. timeout for full chip erase 2 Am29PDL128G Description pin present) PP pin present µs N µ ...
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... CFI specification or CFI publication 100) 0001h 0007h 0000h Erase Block Region 3 Information 0020h (refer to the CFI specification or CFI publication 100) 0000h 0000h 0000h Erase Block Region 4 Information 0000h (refer to the CFI specification or CFI publication 100) 0000h Am29PDL128G Description N 33 ...
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... Not supported Supported Bank Organization 0004h 00 = Data at 4Ah is zero Number of Banks Bank 1 Region Information *0027h X = Number of Sectors in Bank 1 Bank 2 Region Information *0060h X = Number of Sectors in Bank 2 Bank 3 Region Information *0060h X = Number of Sectors in Bank 3 Bank 4 Region Information 0027h X = Number of Sectors in Bank 4 Am29PDL128G Description October 28, 2004 ...
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... Erase Suspend). Enter SecSi Sector/Exit SecSi Sector Command Sequence The SecSi Sector region provides a secured data area containing a random, eight word/four double word electronic serial number (ESN). The system can ac- Am29PDL128G Table 16 show the address and data re- Table 5 shows 35 ...
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... ACC pin must not be left floating or un- connected; inconsistent behavior of the device may re- sult. Figure 3 illustrates the algorithm for the program oper- ation. See the table, on page 57 in and Figure 16 Am29PDL128G Table 14 and Table 16 show the require- Table 14). any operation other than accel- HH “ ...
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... Note: While the Embedded Erase operation is in progress, the system can read data from the non-erasing bank. The system can determine Am29PDL128G “Erase and Program Operations” on page 53 for parame- for timing diagrams. ...
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... For a x16 bit data bus, 4 Password Program commands are required to program the password. For a x32 bit data bus, 2 Password Program commands are required. The user must enter the unlock cycle, Am29PDL128G on page 46 for informa- “Write Operation Status” on page 46 on page 21 and “ ...
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... PPB Lock Bit status is reflected as set, even after a power-on reset cycle. In the Persistent Sector Protec- tion mode, exiting the PPB Lock Bit Set command is accomplished by writing the Read/Reset command. The PPB Lock Bit Set command is permitted if the SecSi sector is enabled. Am29PDL128G -level SecSi Sector CC 39 ...
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... DYB. If the PPB is cleared, setting the DYB protects the sector from programs or erases. Since this is a volatile bit, removing power or resetting the device clears the DYBs. The bank address is latched when the com- mand is written. Am29PDL128G October 28, 2004 ...
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... Sector Protection Status Command The programming of either the PPB or DYB for a given sector or sector group can be verified by writing a Sec- tor Protection Status command to the device. Note: There is no single command to independently verify the programming of a DYB or PPB for a given sector group. Am29PDL128G 41 ...
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... Command valid when device is ready to read array data or when device is in autoselect mode. 14. ACC must 15. Unlock Bypass Entry command is required prior to any Unlock Bypass operation. Unlock Bypass Reset command is required to return to reading array. Am29PDL128G Addr Data Addr Data Addr ...
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... Before issuing erase command, all PPBs should be programmed to prevent PPBs overerasure. 15. DQ1 = 1 if PPB locked unlocked. 16. For all other parts that use the Persistent Protection Bit (excluding PDL640G), the WP address is 00000010 and the EP address is 01000010. Am29PDL128G Addr Data Addr Data Addr XX ...
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... Command is valid when device is ready to read array data or when device is in autoselect mode. 14. ACC must 15. Unlock Bypass Entry command required prior to any Unlock Bypass operation. Unlock Bypass Reset command is required to return to reading array. Am29PDL128G Data Addr Data Addr Data ...
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... Before issuing erase command, all PPBs should be programmed to prevent PPB overerasure. 15. DQ1 = 1 if PPB locked unlocked. 16. For all other parts that use the Persistent Protection Bit (excluding PDL640G), the WP address is 00000010 and the EP address is 01000010. Am29PDL128G Addr Data Addr Data Addr XX ...
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... During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. Figure 6. Data# Polling Algorithm Am29PDL128G Figure 20 shows the Data# Polling timing Yes No Yes ...
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... Note: The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5 on page 46). changes to “1.” See II” on page 48 for more information. Figure 7. Toggle Bit Algorithm Am29PDL128G Figure 21 on page 53 shows the toggle Figure 22 shows the differences on page 48. START ...
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... DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last com- mand might not have been accepted. Table 18 shows the status of DQ3 relative to the other status bits. Am29PDL128G Figure 6). “Sector Erase Command Se- October 28, 2004 ...
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... October 28, 2004 Table 18. Write Operation Status DQ7 DQ5 (Note 2) DQ6 (Note 1) DQ7# Toggle 0 Toggle 1 No toggle Data Data Data DQ7# Toggle on page 48 for more information. Am29PDL128G DQ2 DQ3 (Note 2)) RY/BY# 0 N/A No toggle Toggle 0 0 N/A Toggle 1 Data Data ...
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... +0.8 V –0.5 V –2 200 mA Figure 8. Maximum Negative + –2.0 V for SS 2.0 V Figure 9. Maximum Positive = V ; contact IO CC Am29PDL128G Overshoot Waveform Overshoot Waveform October 28, 2004 ...
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... 3.0 V ± 10 3.0 V ± 10 4.0 mA min I = –2.0 mA min I = –100 µ min (Note CCmax Am29PDL128G Min Typ Max ± 1 ± 1 1.5 5 1 ...
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... Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels INPUTS Steady Changing from Changing from Does Not Apply Center Line is High Impedance State (High Z) Measurement Level Am29PDL128G 70R, 70, 80, 90 Unit 1 TTL gate 0.0–3 ...
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... Test Setup CE Read Toggle and Data# Polling . Addresses Stable t ACC OEH t CE HIGH Z Output Valid Figure 12. Read Operation Timings Am29PDL128G Speed Options 70R Unit Min Max Max Max Max ...
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... AC CHARACTERISTICS A21-A3 A2-A-1 Data Bus CE# OE# Figure 13. Page Read Operation Timings Same Page PACC PACC t ACC Qa Qb Am29PDL128G Ad t PACC Qc Qd October 28, 2004 ...
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... Description Max Max Min Min Min Min Ready Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms t Ready t RP Figure 14. Reset Timings Am29PDL128G All Speed Options Unit 20 µs 500 ns 500 µ ...
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... Output Output DQ31/A-1 Output t ELFH WORD# Output Address DQ31/A-1 Input The falling edge of the last WE# signal t SET ( HOLD table for t and t specifications Am29PDL128G Speed Options 70R Max 5 Max 16 Min Output Address Input t FLQZ Output Output Output t FHQV (t ...
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... RB t Program/Erase Valid to RY/BY# Delay BUSY Notes: 1. Not 100% tested. 2. See the “Erase and Program Operations” October 28, 2004 Word Double Word on page 57 for more information. Am29PDL128G Speed Options 70R Unit Min Min 0 ns ...
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... WPH A0h t BUSY is the true data at the program address. OUT Figure 17. Program Operation Timings Am29PDL128G Read Status Data (last two cycles WHWH1 Status D OUT VHH October 28, 2004 ...
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... Figure 19. Chip/Sector Erase Operation Timings October 28, 2004 555h for chip erase WPH t DH 30h 10 for Chip Erase t BUSY Am29PDL128G Read Status Data WHWH2 Status D OUT t RB “Write Operation Status” on page 46)”. 59 ...
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... OEH GHWL Valid Out t SR/W Read Cycle Complement Complement Status Data Status Data Am29PDL128G Valid PA Valid CPH Valid Valid In In CE# Controlled Write Cycles VA Valid Data True Valid Data True October 28, 2004 ...
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... AHT AS t AHT t ASO t CEPH t OEPH t OE Valid Valid Status Status (first read) (second read) Enter Erase Suspend Program Erase Erase Suspend Suspend Read Program Figure 23. DQ2 vs. DQ6 Am29PDL128G Valid Valid Data Status (stops toggling) Erase Resume Erase Erase Complete Read 61 ...
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... VIDR CE# WE# RY/BY# Figure 24. Temporary Sector Unprotect Timing Diagram Min Min Min Min Program or Erase Command Sequence t RSP Am29PDL128G All Speed Options Unit 500 ns 250 ns 4 µs 4 µ VIDR ...
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... For sector protect For sector unprotect Figure 25. Sector/Sector Block Protect and October 28, 2004 Valid* Valid* 60h Sector Group Protect: 150 µs Sector Group Unprotect Unprotect Timing Diagram Am29PDL128G Valid* Verify 40h Status 63 ...
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... Program Operations” Min Min Min Min Min Min Min Min Min Min Word Typ Double Word Typ Typ Typ on page 57 for more information. Am29PDL128G Speed Options 70R Unit ...
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... SA for sector erase 555 for chip erase Data# Polling GHEL t t WHWH1 CPH t BUSY for program PD for program 55 for erase 30 for sector erase 10 for chip erase is the data written to the device. OUT Am29PDL128G PA DQ7# D OUT 65 ...
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... V, 1,000,000 cycles. CC –100 mA = 3.0 V, one pin at a time. CC Test Setup OUT V IN Test Conditions Am29PDL128G Unit Comments sec Excludes 00h programming prior to erasure (Note 4) sec µs µs µs Excludes system level overhead (Note 5) µs sec , 1,000,000 cycles. Additionally, ...
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... BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER BALL DIAMETER OF SOLDER BALLS IN THE OUTER ROW PARALLEL TO THE DIMENSION, RESPECTIVELY 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW e/2 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. Am29PDL128G ...
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... Changed all references to DPB to DYB. BGA Package Capacitance Replaced TSOP Pin Capacitance with FBGA Capaci- tance data. Table 7. Autoselect Codes (High Voltage Method) Changed the and A3 Sector Protection Verifi- cation fields from Am29PDL128G typi- CC1 typical current to 30 mA. CC6 . October 28, 2004 ...
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... Changed the typicals of the VCC Active Intra-page... 1 and 5 MHz to 1 and 3.5. Changed the min and max of the Voltage for ACC Pro- gram Acceleration to 11.5 and 12.5. Erase and Programming Performance Changed the typical and max of the Sector Erase Time to 0.4 and 5. Am29PDL128G “Memory Array 69 ...
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... ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies Revision B+4 (October 28, 2004) Added Pb-Free options to Ordering information and Valid Combinations. Updated hyperlinks. Am29PDL128G October 28, 2004 ...