AM29PDL310G73WHIN SPANSION [SPANSION], AM29PDL310G73WHIN Datasheet
AM29PDL310G73WHIN
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AM29PDL310G73WHIN Summary of contents
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Am29PDL640G Data Sheet Continuity of Specifications Continuity of Ordering Part Numbers For More Information Publication Number 26573 Revision B Amendment +1 Issue Date February 26, 2003 ...
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PRELIMINARY Am29PDL640G 64 Megabit ( 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory with Enhanced VersatileIO DISTINCTIVE CHARACTERISTICS ARCHITECTURAL ADVANTAGES ■ 64 Mbit Page Mode device — Page size of 8 words: Fast page read access from random ...
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GENERAL DESCRIPTION The Am29PDL640G Mbit, 3.0 volt-only Page Mode and Simultaneous Read/Write Flash memory device orga- nized as 4 Mwords. The device is offered in 63- or 80-ball Fine-pitch BGA packages. The word-wide data (x16) ap- pears ...
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TABLE OF CONTENTS Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5 Block Diagram . . . . . . . . . . ...
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Figure 23. Sector/Sector Block Protect and Unprotect Timing Diagram .............................................................. 52 Alternate CE# Controlled Erase and Program Operations ..... 53 Figure 24. Alternate CE# Controlled Write (Erase/Program) Operation Timings........................................................................... 54 Erase And Programming Performance . . . . . . ...
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PRODUCT SELECTOR GUIDE Part Number 2.7–3 Speed Option V = 2.7–3 Max Access Time ACC Max CE# Access Max Page Access ...
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SIMULTANEOUS READ/WRITE BLOCK DIAGRAM Mux A21–A0 RY/BY# A21–A0 RESET# STATE WE# CONTROL CE# & WP#/ACC COMMAND REGISTER DQ0–DQ15 A21–A0 Mux OE# Bank A Bank ...
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CONNECTION DIAGRAMS A13 A12 WE# RESET# C4 RY/BY# WP#/ACC C3 A7 A17 February 26, ...
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CONNECTION DIAGRAMS A13 A12 WE# RESET RY/BY# WP#/ACC A17 NC Balls ...
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PIN DESCRIPTION A21– Addresses DQ15–DQ0 = 16 Data Inputs/Outputs CE# = Chip Enable OE# = Output Enable WE# = Write Enable WP#/ACC = Hardware Write Protect/Program Acceleration Input RESET# = Hardware Reset Pin, Active Low RY/BY# = Ready/Busy ...
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ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following: Am29PDL640G DEVICE NUMBER/DESCRIPTION Am29PDL640G 64 Megabit ( ...
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DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory loca- tion. The register is a latch ...
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Here again, CE# selects ACC CE the device and OE# is the output control and should be used to gate data to the output inputs ...
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The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V (Note that this is a more restricted voltage range than CE# and RESET# are held ...
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Table 4. Am29PDL640G Sector Architecture Sector Sector Bank Sector Address Size A21–A12 (Kwords) SA23 0010000xxx 32 SA24 0010001xxx 32 SA25 0010010xxx 32 SA26 0010011xxx 32 SA27 0010100xxx 32 SA28 0010101xxx 32 SA29 0010110xxx 32 SA30 0010111xxx 32 SA31 0011000xxx 32 ...
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Table 4. Am29PDL640G Sector Architecture Sector Sector Bank Sector Address Size A21–A12 (Kwords) SA119 1110000xxx 32 SA120 1110001xxx 32 SA121 1110010xxx 32 SA122 1110011xxx 32 SA123 1110100xxx 32 SA124 1110101xxx 32 SA125 1110110xxx 32 SA126 1110111xxx 32 SA127 1111000xxx 32 ...
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Table 7. Autoselect Codes (High Voltage Method) Description CE# OE# WE# Manufacturer ID AMD Read Cycle 1 Read Cycle 2 Read Cycle 3 Sector Protection Verification SecSi Indicator Bit L L ...
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SECTOR PROTECTION The Am29PDL640G features several levels of sector protection, which can disable both the program and erase operations in certain sectors or sector groups: Persistent Sector Protection A command sector protection method that replaces the old 12 V controlled ...
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This allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are needed. The DYBs maybe set or cleared ...
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When the device is first powered on, or comes out of a reset cycle, the PPB Lock bit set to the locked state, rather than cleared to the unlocked state. ■ The only means to clear the PPB Lock ...
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If the Password Mode Locking Bit is not set, including Persistent Protection Mode, the PPB Lock Bit is cleared after power-up or hardware reset. The PPB Lock Bit is set by issuing the PPB Lock Bit Set com- mand. Once ...
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START PLSCNT = 1 RESET Wait 4 µs No First Write Temporary Sector Cycle = 60h? Unprotect Mode Yes Set up sector address Sector Protect: Write 60h to sector address with A6-A0 = 0111010 Wait 100 µs ...
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Temporary Sector Unprotect This feature allows temporary unprotection of previ- ously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RE- SET# pin During this mode, formerly protected ID sectors can ...
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Note that the accelerated programming (ACC) and unlock bypass functions are not available when programming the SecSi Sector. The SecSi Sector area can be protected using one of the following procedures: ■ ...
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Embedded Program or embedded Erase al- gorithm. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data ...
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Table 10. CFI Query Identification String Addresses Data 10h 0051h 11h 0052h 12h 0059h 13h 0002h 14h 0000h 15h 0040h 16h 0000h 17h 0000h 18h 0000h 19h 0000h 1Ah 0000h Addresses Data 1Bh 0027h 1Ch 0031h 1Dh 0000h 1Eh 0000h ...
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Addresses Data 27h 0017h 28h 0001h 29h 0000h 2Ah 0000h 2Bh 0000h 2Ch 0003h 2Dh 0007h 2Eh 0000h 2Fh 0020h 30h 0000h 31h 007Dh 32h 0000h 33h 0000h 34h 0001h 35h 0007h 36h 0000h 37h 0020h 38h 0000h 39h 0000h ...
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Table 13. Primary Vendor-Specific Extended Query Addresses Data 40h 0050h 41h 0052h 42h 0049h 43h 0031h 44h 0033h 45h 0004h 46h 0002h 47h 0001h 48h 0001h 49h 0007h 4Ah 0077h 4Bh 0000h 4Ch 0002h 4Dh 0085h 4Eh 0095h 4Fh 0001h ...
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COMMAND DEFINITIONS Writing specific address and data commands or se- quences into the command register initiates device op- erations. Table 14 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence ...
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Enter SecSi™ Sector/Exit SecSi Sector Command Sequence The SecSi Sector region provides a secured data area containing a random, eight word electronic serial num- ber (ESN). The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi ...
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Write Program Command Sequence Data Poll from System Embedded Program algorithm in progress Verify Data? No Increment Address Last Address? Programming Completed Note: See Table 14 for program command sequence. Figure 4. Program Operation Chip Erase Command Sequence Chip erase ...
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The system can de- termine the status of the erase operation by reading DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. Refer to the Write Operation Status mation on these status bits. Once the ...
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There are no provisions for entering the 2-cycle unlock cycle, the password program command, and all the password data. There is no special addressing order required for programming the password. Also, when the password is ...
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Password Unlock Command The Password Unlock command is used to clear the PPB Lock Bit so that the PPBs can be unlocked for modification, thereby allowing the PPBs to become ac- cessible for modification. The exact password must be entered ...
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Command Definitions Tables Table 14. Memory Array Command Definitions Command (Notes) Read (5) 1 Reset (6) 1 Manufacturer ID 4 Device ID (10) 6 Autoselect SecSi Sector Factory 4 (Note 7) Protect (8) Sector Group Protect 4 Verify (9) Program ...
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Table 15. Sector Protection Command Definitions Command (Notes) Reset 1 SecSi Sector Entry 3 SecSi Sector Exit 4 SecSi Protection Bit Program ( SecSi Protection Bit Status 4 Password Program ( Password Verify (8, 9) ...
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WRITE OPERATION STATUS The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 16 and the following subsections describe the function of these bits. DQ7 and DQ6 each ...
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RY/BY#: Ready/Busy# The RY/BY dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since ...
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DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indi- cates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit ...
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Status Embedded Program Algorithm Standard Mode Embedded Erase Algorithm Erase Suspended Sector Erase-Suspend- Erase Read Suspend Non-Erase Mode Suspended Sector Erase-Suspend-Program Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C Ambient Temperature with Power Applied . . . . . . . . . . ...
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DC CHARACTERISTICS CMOS Compatible Parameter Parameter Description Symbol I Input Load Current LI I A9, OE#, RESET# Input Load Current LIT I Output Leakage Current Active Read Current (Notes 1, 2) CC1 Active Write ...
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TEST CONDITIONS Device Under Test C 6.2 kΩ L Note: Diodes are IN3064 or equivalent Figure 10. Test Setup KEY TO SWITCHING WAVEFORMS WAVEFORM Don’t Care, Any Change Permitted 3.0 V 1.5 V Input 0.0 V Figure 11. Input Waveforms ...
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AC CHARACTERISTICS Read-Only Operations Parameter JEDEC Std. Description t t Read Cycle Time (Note 1) AVAV Address to Output Delay AVQV ACC t t Chip Enable to Output Delay ELQV CE t Page Access Time PACC t ...
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AC CHARACTERISTICS A21-A3 A2-A0 Data CE# OE# Figure 13. Page Read Operation Timings Same Page PACC PACC t ACC Qa Qb Am29PDL640G Ad ...
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AC CHARACTERISTICS Hardware Reset (RESET#) Parameter JEDEC Std RESET# Pin Low (During Embedded Algorithms) t Ready to Read Mode (See Note) RESET# Pin Low (NOT During Embedded t Ready Algorithms) to Read Mode (See Note) t RESET# Pulse Width RP ...
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AC CHARACTERISTICS Erase and Program Operations Parameter JEDEC Std Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL AS Address Setup Time to OE# low during toggle bit t ASO polling t t ...
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AC CHARACTERISTICS Program Command Sequence (last two cycles Addresses 555h CE# OE# WE Data RY/BY VCS Notes program address program data ...
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AC CHARACTERISTICS Erase Command Sequence (last two cycles Addresses 2AAh CE Data 55h RY/BY# t VCS V CC Note sector address (for Sector Erase Valid Address ...
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AC CHARACTERISTICS t WC Valid PA Addresses CE# OE WE# t WPH t DS Valid Data In WE# Controlled Write Cycle Figure 18. Back-to-back Read/Write Cycle Timings t RC Addresses VA t ACC t ...
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AC CHARACTERISTICS Addresses CE# t OEH WE# OE Valid Data DQ6/DQ2 RY/BY# Note Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read ...
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AC CHARACTERISTICS Temporary Sector Unprotect Parameter JEDEC Std Description t V Rise and Fall Time (See Note) VIDR Rise and Fall Time (See Note) VHH HH RESET# Setup Time for Temporary Sector t RSP Unprotect RESET# Hold ...
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AC CHARACTERISTICS RESET# SA, A6, A1, A0 Sector Group Protect/Unprotect Data 60h 1 µs CE# WE# OE# * For sector protect For sector unprotect ...
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AC CHARACTERISTICS Alternate CE# Controlled Erase and Program Operations Parameter JEDEC Std. Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL Address Hold Time ELAX Data Setup ...
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AC CHARACTERISTICS 555 for program 2AA for erase Addresses WE# OE# CE Data t RH RESET# RY/BY# Notes: 1. Figure indicates last two bus cycles of a program or erase operation ...
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ERASE AND PROGRAMMING PERFORMANCE Parameter Sector Erase Time Chip Erase Time Word Program Time Accelerated Word Program Time Chip Program Time (Note 3) Notes: 1. Typical program and erase times assume the following conditions: 25°C, 3 programming typicals ...
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PHYSICAL DIMENSIONS FBE080—80-Ball Fine-pitch Ball Grid Array package D A1 CORNER INDEX MARK 10 TOP VIEW A A1 SEATING PLANE SIDE VIEW PACKAGE FBE 080 JEDEC N/A 10. 11.95 mm PACKAGE SYMBOL MIN. NOM. ...
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PHYSICAL DIMENSIONS FBE063—63-Ball Fine-pitch Ball Grid Array package February 26, 2003 Am29PDL640G Dwg rev AF; 10/99 57 ...
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REVISION SUMMARY July 12, 2002 Initial release. Revision A+1 (July 29, 2002) Global Changed all references to DPB to DYB Table 7. Autoselect Codes (High Voltage Method) Changed the and A3 Sector Protection Verifi- cation fields from ...
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SecSi Sector Flash Memory Region, and Enter SecSi Sector/Exit SecSi Sector Command Sequence Noted that the ACC function and unlock bypass modes are not available when the SecSi sector is enabled. Byte/Word Program Command Sequence, Sector Erase Command Sequence, and ...
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