HDSP-390X Agilent(Hewlett-Packard), HDSP-390X Datasheet
HDSP-390X
Related parts for HDSP-390X
HDSP-390X Summary of contents
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Low Cost Gigabit Rate Transmit/Receive Chip Set Technical Data Features • Transparent, Extended Ribbon Cable Replacement • Implemented in a Low Cost Aluminum M-Quad 80 Package • High-Speed Serial Rate 150- 1500 MBaud • Standard 100K ECL Interface 16, 17, ...
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When data is not available to send, the link maintains synchronization by transmitting fill frames. Two (training) fill frames are reserved for handshaking during link startup. User control space is also sup- ported. If Control ...
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Typical Applications The HDMP-1012/1014 chipset was designed for ease of use and flexibility. This allows the customer to tailor the use of this product, through the configura- tion of the link, based on their specific system requirements and application needs. ...
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For timing diagrams for the standard configurations, see the Appendix section entitled Link Configuration Examples. The HDMP-1012/1014 chipset can support serial transmission rates from 150 MBd to 1.5 GBd for each of these configurations. The chipset requires the user to ...
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HDMP-1012 (Tx), HDMP-1014 (Rx) Typical Operating Rates For 16 Bit Mode + -4 -5 Parallel Word Rate (Mword/sec) DIV1 DIV0 Range 75.0 (max ...
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INPUT LATCH ED FF CONTROL LOGIC CAV* + C-FIELD ENCODER DAV* FLAG D0-D19 D-FIELD ENCODER RST* Figure 4. HDMP-1012 Transmitter Block Diagram. HDMP-1012 Tx Block Diagram The HDMP-1012 was designed to accept bit wide parallel data and ...
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The type of fill frames sent (FF0 or FF1) is determined by the FF input duplex system normally connected to the Rx’s STAT1 pin. The C-Field Encoder, based on the inputs ...
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DIN INPUT SELECT LIN PHASE / FDIS FREQ DETECT PH1 CAP0 FILTER 0.1 µF CAP1 VCO Figure 5. HDMP-1014 Receiver Block Diagram. HDMP-1014 Rx Block Diagram The HDMP-1014 receiver was designed to convert a serial data signal sent from the ...
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Clock Select The Clock Select accepts the high speed digital signal from the VCO and outputs an internal high speed serial clock. The VCO frequency is divided, based on the DIV1/DIV0 inputs, to the input signal’s frequency range. The Clock ...
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HDMP-1012 (Tx) Timing Figure 6 shows the Tx timing diagram. Under normal operations, the Tx PLL locks an internally generated clock to the incoming STRBIN. The incoming data, D0-D19, ED, FF, DAV*, CAV*, and FLAG, are latched by this internal ...
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HDMP-1014 (Rx) Timing Figure 7 is the Rx timing diagram when the internal PLL is locked to the incoming serial data. The BCLK’s frequency is the same as the input data rate. The size of the input data frame can ...
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HDMP-1012 (Tx), HDMP-1014 (Rx) DC Electrical Specifications +85 C, GND = Ground, V Symbol V ECL Input High Voltage Level, Guaranteed high signal IH,ECL for all inputs V ECL Input Low Voltage Level, Guaranteed low ...
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HDMP-1012 (Tx), HDMP-1014 (Rx) Absolute Maximum Ratings except as specified. Operation in excess of any one of these conditions may result in permanent damage to this device. Symbol V Supply Voltage EE V ECL Input Voltage ...
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PIN #1 ID CAP0B 1 CAP0A 2 CAP1A 3 CAP1B HGND 7 STRBIN 8 STRBIN* 9 HCLKON 10 HCLK 11 HCLK* 12 HGND 13 LOUT 14 LOUT* 15 LOOPEN 16 DOUT 17 DOUT* 18 DIV0 ...
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Tx I/O Definition Name Pin Type CAP0A 2 C Loop Filter Capacitor: CAP0A should be shorted to CAP0B. CAP1A CAP0B 1 should be shorted to CAP1B. A loop filter capacitor of 0.1 F must be CAP1A 3 connected across the ...
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Tx I/O Definition (cont’d.) Name Pin Type EHCLKSEL 78 I-ECL EHCLK Enable: When active, this input causes the STRBIN inputs to be used for the transmit serial clock, rather than the internal VCO clock. This is useful for generating extremely ...
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Tx I/O Definition (cont’d.) Name Pin Type INV 25 O-ECL Invert Signal: A high value of INV implies that the current frame is being sent inverted to maintain long-term DC balance. With a buffer, or pulled down with a 1K ...
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Tx I/O Definition (cont’d.) Name Pin Type STRBOUT 76 O-ECL Frame-rate Data Clock Output: This output is always a frame rate clock derived from STRBIN. With a buffer or pulled down with a 1K resistor to V oscilloscope for examining ...
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Rx I/O Definition Name Pin Type ACTIVE 25 I-ECL Chip Enable: This input is normally driven by the Rx state machine output. The ACTIVE signal is internally retimed by STRBOUT and presented to the user as the LINKRDY signal. This ...
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Rx I/O Definition (cont’d.) Name Pin Type ECLGND 32 S ECL Ground: Normally 0 volts. This ground is used for the ECL pad 52 drivers. For best performance it is suggested that coupling of the noisy 53 ECLGND to the ...
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Rx I/O Definition (cont’d.) Name Pin Type LIN LIN* 18 I-H50 Loop Back Serial Data Input: Use this input when LOOPEN is 17 active. Unlike the DIN, DIN* inputs, this input does not have a cable equalizer. In normal usage, ...
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Rx I/O Definition (cont’d.) Name Pin Type Power: Normally -5 V +10 594 Signal ...
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Mechanical Dimensions and Surface Mount Assembly Recommendations Both the HDMP-1012 and HDMP- 1014 are implemented in an industry standard M-Quad 80 package. The package outline M-Quad 80 Package Information Item Package Material Lead Finish Material Lead Finish Thickness Lead Coplanarity ...
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Appendix I: Additional Internal Architecture Information Line Code Description The HDMP-1012/1014 line code is Conditional Invert Master Transition (CIMT), illustrated in Figure 11. The CIMT line uses three types of frames: data frames, control frames, and fill frames. Fill frames ...
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HDMP-1012 (Tx), HDMP-1014 (Rx) Operating Modes M20SEL FLAGSEL HDMP-1012 (Tx), HDMP-1014 (Rx) Data Frame Structure M20SEL Not Asserted (16 bit data mode) Data Status Flag bit True 0 Inverted 0 True 1 ...
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HDMP-1012 (Tx), HDMP-1014 (Rx) Control Frame Structure M20SEL Not Asserted (16 bit mode) D-Field D15 ...
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HDMP-1014 (Rx) Detectable Error States M20SEL Not Asserted (16 bit mode) D-Field xxxxxxx xx xxxxxxx xx xxxxxxx 0x xxxxxxx 11 xxxxxxx xx xxxxxxx xx HDMP-1014 (Rx) Detectable Error States M20SEL Asserted (20 bit mode) D-Field xxxxxxxxx xx xxxxxxxxx xx xxxxxxxxx ...
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The Output Select block allows the user to select between two sets of differential high speed serial outputs. This feature is useful for loop back testing. If LOOPEN is high, LOUT is ...
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The lock detect circuit samples STRBIN with phase shifted versions of STRBOUT. If the samples are not the proper values, the LOCKED signal goes low and stays low for at least two frames. Rx Operation Principles The HDMP-1014 (Rx) is ...
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FDIS FREQ SIN PHASE STRBOUT CLOCK GEN Figure 14. HDMP-1014 (Rx) Phase-Locked Loop. the frequency detector to align its internal clock with the rising edge of FF0/FF1. Once frequency lock is accomplished, FDIS can be set to 1, then the ...
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If iERR=1, then ERROR=1. • Fill Frame is detected, then FLAG=0. • Data Frame is detected, then FLAG=iFLAG, and iFLAG should alternate between 0 and 1, starting with ...
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FF0 1 ERROR RESET 2 Figure 15. HDMP-1014 (Rx) State Machine State Diagram. When the local port is in State the reset state, where both local Tx and Rx parallel interfaces are disabled. The local ...
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Tx DATA INTERFACE POWER-ON RESET Rx DATA INTERFACE Figure 16. Full Duplex Configuration. Appendix II: Link Configuration Examples This section shows some application examples using the HDMP-1012/1014 chipset. Refer to I/O Definition for detailed circuit-level interconnection. This guide is intended ...
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FF1, causing STAT0 to go high, which asserts the enable data (ED) pin on the Tx. The ED signal is retimed to signify to the host that the Tx is ready to send data (RFD). Other configurations for duplex ...
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LOCKED line can be eliminated. Simplex Method II. Simplex with Periodic Sync Pulse. Another configuration of simplex operation is shown in Figure 17b. For frame lock, the Rx normally relies on either FF0 or FF1. In this example, the ...
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Timing. Since the PLL of the Tx is designed with a very high-gain frequency/phase detector, the relative alignment of the internal clock and STRBIN is very tight, and is insensitive to temperature and other variations. The observed external changes are ...
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The setup and hold times are referenced to 1/2 frame period of D0-D19 deg, from the edges of STRBIN. The multiplexer delay should be mux considered for timing ...
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V EE PIN 1 CAP0B CAP0A D1 C2 CAP1A CAP1B HGND TOP VIEW HGND GND GND PIN 1 CAP0B CAP0A D1 C2 CAP1A CAP1B GND TOP ...
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I-ECL ECL OUTPUT Figure 21. I-ECL and O-ECL Simplified Circuit Schematic. found in the data sheet under I/O Definitions. I-ECL and O-ECL These I/O are designed to interface directly to ...
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ECL swings directly into 50 . The output impedance is matched to 50 with a VSWR of less than 2:1 to above 2 GHz. This output is ideal for driving the I- H50 input through a 50 cable and ...
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Likewise, the Vtt plane must also be bypassed equally well. In the positive 5 V supply configuration, the logic outputs are in the PECL (positive ECL) states. Commercial translation chips are available which will translate PECL between TTL and CMOS. ...
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LOOPEN = 0/1 selects either the normal data or the loop channels the I/O. MDFSEL = 0/1 selects the Tx single or double frame modes. ECHKSEL = 0/1 selects either to lock onto a frame-rate clock at STRBIN or to ...