K9F2808Q0B Samsung semiconductor, K9F2808Q0B Datasheet
K9F2808Q0B
Related parts for K9F2808Q0B
K9F2808Q0B Summary of contents
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... Changed WE High Hold time(tWH) from 15ns to 20ns 0.3 1. Device Code is changed - TBGA package information : ’B’ --> ’D’ ex) K9F2808Q0B-BCB0 ,BIB0 --> K9F2808Q0B-DCB0,DIB0 K9F2808U0B-BCB0 ,BIB0 --> K9F2808Q0B-DCB0,DIB0 K9F2808Q0B(1.8 device) is changed IH IL Input High Voltage Input Low Voltage, All inputs Input High Voltage Input Low Voltage, All inputs Note : For more detailed features and specifications including FAQ, please refer to Samsung’ ...
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... Parameters are changed in 1.8V part(K9F2808Q0B tRP is changed from 25ns to 35ns - tWB is changed from 100ns to 150ns - tREA is changed from 40ns to 45ns Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site. ...
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... Data in a page can be read out at 70ns/50ns(K9F2808Q0B:70ns, K9F2808U0B:50ns) cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write control automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even write-intensive systems can take advantage of the K9F2808X0B’ ...
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... K9F2808U0B-YCB0,YIB0 K9F2808Q0B-DCB0,DIB0 K9F2808U0B-VCB0,VIB0 K9F2808U0B-DCB0,DIB0 PIN CONFIGURATION (TSOP1) N.C N.C N.C N.C N.C GND R N.C N.C Vcc Vss N.C N.C CLE ALE WE WP N.C N.C N.C N.C N.C PACKAGE DIMENSIONS 48-PIN LEAD PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE( TSOP1 - 1220F #1 #24 ¡Æ 0~8 0.45~0.75 0.018~0.030 K9F2808U0B-YCB0/YIB0 ...
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... K9F2808U0B-YCB0,YIB0 K9F2808Q0B-DCB0,DIB0 K9F2808U0B-VCB0,VIB0 K9F2808U0B-DCB0,DIB0 PIN CONFIGURATION (TBGA) PACKAGE DIMENSIONS 63-Ball TBGA (measured in millimeters) Top View 9.00 0.10 #A1 K9F2808X0B-DCB0/DIB0 DNU DNU DNU DNU DNU /WP ALE NC /CE /WE R/B NC /RE CLE I/ Vcc ...
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... K9F2808U0B-YCB0,YIB0 K9F2808Q0B-DCB0,DIB0 K9F2808U0B-VCB0,VIB0 K9F2808U0B-DCB0,DIB0 PIN CONFIGURATION (WSOP1) N.C 1 N.C 2 DNU 3 N.C 4 N.C 5 N DNU 10 N.C 11 Vcc 12 Vss 13 N.C 14 DNU 15 CLE 16 ALE N.C 20 N.C 21 DNU 22 N.C 23 N.C 24 PACKAGE DIMENSIONS 48-PIN LEAD PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE ( WSOP1 - 1217F ...
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... K9F2808U0B-YCB0,YIB0 K9F2808Q0B-DCB0,DIB0 K9F2808U0B-VCB0,VIB0 K9F2808U0B-DCB0,DIB0 PIN DESCRIPTION Pin Name DATA INPUTS/OUTPUTS I/O ~ I/O The I/O pins are used to input command, address and data, and to output data during read operations. The 0 7 I/O pins float to high-z when the chip is deselected or when the outputs are disabled. COMMAND LATCH ENABLE CLE The CLE input controls the activating path for commands sent to the command register ...
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... K9F2808U0B-YCB0,YIB0 K9F2808Q0B-DCB0,DIB0 K9F2808U0B-VCB0,VIB0 K9F2808U0B-DCB0,DIB0 Figure 1. FUNCTIONAL BLOCK DIAGRAM Command CE Control Logic RE & High Voltage WE CLE ALE Figure 2. ARRAY ORGANIZATION 32K Pages 1st half Page Register (=1,024 Blocks) (=256 Bytes) 512B Byte Page Register 512 Byte ...
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... K9F2808U0B-YCB0,YIB0 K9F2808Q0B-DCB0,DIB0 K9F2808U0B-VCB0,VIB0 K9F2808U0B-DCB0,DIB0 PRODUCT INTRODUCTION The K9F2808X0B is a 132Mbit(138,412,032 bit) memory organized as 32,768 rows(pages) by 528 columns. Spare 16 columns are located in 512 to 527 column address. A 528-byte data register is connected to memory cell arrays accommodating data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made cells that are serially connected like NAND structure ...
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... K9F2808U0B: tRC=50ns - - - - CE =0V CE=V -0.2, WP =0V Vcc(max Vcc(max) - OUT I/O pins VccQ-0.4 Except I/O pins V -0 -0.3 K9F2808Q0B :I =-100 Q-0.1 CC K9F2808U0B :I =-400 A OH K9F2808Q0B :I =100uA OL - K9F2808U0B :I =2.1mA OL K9F2808Q0B :V =0. K9F2808U0B :V =0. FLASH MEMORY Rating K9F2808U0B(3.3V) -0 4.6 -0 4.6 -0 4.6 - 125 - 125 - 150 +2.0V for periods < ...
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... The 1st block, which is placed on 00h block address, is fully guaranteed valid block, does not require Error Correct i on. AC TEST CONDITION (K9F2808X0B-YCB0, DCB0 :TA K9F2808X0B-YIB0,DIB0:TA=- K9F2808Q0B : Vcc=1.7V~1.9V , K9F2808U0B : Vcc=2.7V~3.6V unless otherwise noted) Parameter Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels K9F2808Q0B:Output Load (VccQ:1 ...
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... REH WHR t - RST CRY - t 100 CEH 12 FLASH MEMORY K9F2808U0B Min Max K9F2808Q0B K9F2808U0B Max Min Max 150 - 100 - (1) - 5/10/500 5/10/500 100 - 100 50 +tr(R/B) ( +tr(R/B) - ...
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... K9F2808U0B-YCB0,YIB0 K9F2808Q0B-DCB0,DIB0 K9F2808U0B-VCB0,VIB0 K9F2808U0B-DCB0,DIB0 NAND Flash Technical Notes Invalid Block(s) Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The infor- mation regarding invalid block( called as the invalid block information. Devices ,regardless of having invalid block(s), have the same quality level because all valid blocks have same AC and DC characteristics. An invalid block(s) does not affect the perfor- mance of valid block(s) because it’ ...
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... K9F2808U0B-YCB0,YIB0 K9F2808Q0B-DCB0,DIB0 K9F2808U0B-VCB0,VIB0 K9F2808U0B-DCB0,DIB0 NAND Flash Technical Notes (Continued) Error in write or read operation Within its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for actual data. The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail- ure after erase or program, block replacement should be done ...
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... K9F2808U0B-YCB0,YIB0 K9F2808Q0B-DCB0,DIB0 K9F2808U0B-VCB0,VIB0 K9F2808U0B-DCB0,DIB0 NAND Flash Technical Notes (Continued) Erase Flow Chart Write 60h Write Block Address Write D0h Read Status Register I R Erase Error I Erase Completed : If erase operation results in an error, map out * the failing block and replace it with another block. ...
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... K9F2808U0B-YCB0,YIB0 K9F2808Q0B-DCB0,DIB0 K9F2808U0B-VCB0,VIB0 K9F2808U0B-DCB0,DIB0 Pointer Operation of K9F2808X0B Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. ’00h’ command sets the pointer to ’A’ area(0~255byte), ’01h’ command sets the pointer to ’B’ area(256~511byte), and ’50h’ command sets the pointer to ’ ...
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... K9F2808U0B-YCB0,YIB0 K9F2808Q0B-DCB0,DIB0 K9F2808U0B-VCB0,VIB0 K9F2808U0B-DCB0,DIB0 System Interface Using CE don’t-care. For an easier system interface, CE may be inactive during data-loading or sequential data-reading as shown below. The internal 528byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and read- ing would provide significant saving in power consumption ...
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... K9F2808U0B-YCB0,YIB0 K9F2808Q0B-DCB0,DIB0 K9F2808U0B-VCB0,VIB0 K9F2808U0B-DCB0,DIB0 * Command Latch Cycle CLE CE WE ALE I Address Latch Cycle CLE CE WE ALE I CLH CLS ALH ALS Command t CLS ALH ALS t ALS t DH ...
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... K9F2808U0B-YCB0,YIB0 K9F2808Q0B-DCB0,DIB0 K9F2808U0B-VCB0,VIB0 K9F2808U0B-DCB0,DIB0 * Input Data Latch Cycle CLE CE t ALS ALE I Serial Access Cycle after Read R/B NOTES : Transition is measured 200mV from steady state voltage with load DIN 0 DIN 1 ...
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... K9F2808U0B-YCB0,YIB0 K9F2808Q0B-DCB0,DIB0 K9F2808U0B-VCB0,VIB0 K9F2808U0B-DCB0,DIB0 * Status Read Cycle CLE I READ1 OPERATION (READ ONE PAGE) CLE ALE 00h or 01h I Column Address R/B NOTE : 1) is only valid on K9F2808U0B_Y or K9F2808U0B_V t CLR CLS t CLH WHR ...
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... K9F2808U0B-YCB0,YIB0 K9F2808Q0B-DCB0,DIB0 K9F2808U0B-VCB0,VIB0 K9F2808U0B-DCB0,DIB0 READ2 OPERATION (READ ONE PAGE) CLE CE WE ALE RE I/O ~ 50h R/B M Address PAGE PROGRAM OPERATION CLE ALE RE I/O ~ 80h Sequential Data Column Input Command Address R ...
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... I 90h Read ID Command (ERASE ONE BLOCK DOh Busy Erase Command t CLR t AR1 t REA 00h Address. 1cycle K9F2808Q0B K9F2808U0B 22 FLASH MEMORY t BERS 70h I/O 0 Read Status I/O 0 Command Device ECh Code* Maker Code Device Code Device Device Code* 33h ...
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... The system controller can detect the completion of this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the registers, they may be read out by sequential RE pulse of 70ns/50n(K9F2808Q0B:70ns, K9F2808U0B:50ns) period cycle. High to low transitions of the RE clock take out the data from the selected column address up to the last column address ...
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... K9F2808U0B-YCB0,YIB0 K9F2808Q0B-DCB0,DIB0 K9F2808U0B-VCB0,VIB0 K9F2808U0B-DCB0,DIB0 Figure 8. Read2 Operation CLE CE WE ALE R/B RE 50h Start Add.(3Cycle) I & Don t Care) Figure 7-1. Sequential Row Read1 Operation (only for K9F2808U0B-Y and K9F2808U0B-V, valid within a block) R/B I 00h Start Add.(3Cycle) 01h ...
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... K9F2808U0B-YCB0,YIB0 K9F2808Q0B-DCB0,DIB0 K9F2808U0B-VCB0,VIB0 K9F2808U0B-DCB0,DIB0 Figure 8-1. Sequential Row Read2 Operation (GND Input=Fixed Low) (only for K9F2808U0B-Y and K9F2808U0B-V, valid within a block) R/B I/O ~ Start Add.(3Cycle 50h & Don t Care) PAGE PROGRAM The device is programmed basically on a page basis, but it allows multiple partial page program of one byte or consecutive bytes up to 528 single page program cycle ...
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... K9F2808U0B-YCB0,YIB0 K9F2808Q0B-DCB0,DIB0 K9F2808U0B-VCB0,VIB0 K9F2808U0B-DCB0,DIB0 BLOCK ERASE The Erase operation is done on a block(16K Bytes) basis. Block Erase is executed by entering Erase Setup command(60h) and 2 cycle block addresses and Erase Confirm command(D0h). Only address A14 to A23 is valid while A9 to A13 is ignored. This two- step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise condition ...
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... Figure 12. RESET Operation R/B I FFh Table4. Device Status Operation Mode t CLR t CEA t AR1 t WHR t REA 00h ECh Maker code Device K9F2808Q0B K9F2808U0B t RST After Power-up Read 1 27 FLASH MEMORY Device Code* Device code Device Code* 33h 73h After Reset Waiting for next command ...
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... K9F2808U0B-YCB0,YIB0 K9F2808Q0B-DCB0,DIB0 K9F2808U0B-VCB0,VIB0 K9F2808U0B-DCB0,DIB0 READY/BUSY The device has output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command reg- ister or random read is started after address loading. It returns to high when the internal controller has finished the operatio n. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied ...
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... Data Protection & Powerup sequence The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 1.1V/2V(K9F2808Q0B:1.1V, K9F2808U0B:2V). WP pin provides hardware pro- tection and is recommended to be kept at V before internal circuit gets ready for any command sequences as shown in Figure 14. The two step command sequence for program/ erase provides additional software protection ...