CYIL1SM1300AA_09 CYPRESS [Cypress Semiconductor], CYIL1SM1300AA_09 Datasheet - Page 14

• Manufacturer Part Number: CYIL1SM1300AA_09
• Description: LUPA-1300 1.3 MPxl High Speed CMOS Image Sensor
• Manufacturer: CYPRESS [Cypress Semiconductor]

Timing
Timing of the Pixel Array
The timing of the image sensor can be divided in two major parts. The first part of the timing is related with the timing of the pixel
array. This implies the control of the integration time, the synchronous shutter operation, and the sampling of the pixel information
onto the memory element inside each pixel. The signals needed for this control are described earlier and
of the internal signals.
Table 10. Typical Timings of Pixel Array
The timing of the pixel array is straightforward. Before the frame
is read, the information on the photodiode needs to be stored
onto the memory element inside the pixels. This is done by
means of the signals Vmemory, Precharge and Sample.
Precharge sets the memory element to a reference level and
Sample stores the photodiode information onto the memory
element. Vmemory pumps up this value to reduce the loss of
signal in the pixel and this signal must be the envelop of
Precharge and Sample. After Vmemory is high again, the
readout of the pixel array can start. The frame blanking time or
frame overhead time is thus the time that Vmemory is low, which
is about 5 sec. Once the readout starts, the photodiodes can all
be initialised by reset for the next integration time. The duration
of the reset pulse indicates the integration time for the next
frame. The longer this duration, the shorter the integration time
becomes. Maximum integration time is thus the time it takes to
readout the frame, minus the minimum pulse for reset, which is
Document Number: 38-05711 Rev. *D
a
b
c
d
e
f
Symbol
Mem_HL
MEM_HL -Precharge
Precharge
Sample
Precharge-Sample
Integration time
Figure 13. Timing of pixel array. All External Signals are Digital Signals Between 0 and 5V.
Figure 13
Name
should make the timing of the external signals clear.
Reset_ds Only Required in Case Dual Slope is Desired.
> 5 μsec
> 200 nsec
> 500 nsec
> 3.9 μsec
> 400 nsec
> 2 μsec
Value
preferred not to be less than 10 sec. The minimal integration time
is the minimal time between the falling edge of reset and the
rising edge of sample. Keeping the slow fall times of the corre-
sponding internal generated signals, a minimal integration time
is about 2 sec. An additional reset pulse can be given during
integration by Reset_ds to implement the double slope
integration mode.
Readout of Pixel Array
Once the photodiode information is stored into the memory
element in each pixel, the total pixel array of 1280 * 1024 needs
to be readout in less than 2 msec (2 msec - frame overhead time
= 1995 μsec). Additionally, it is possible that only a part of the
whole frame is read out. This is controlled by the starting address
that has to be downloaded and from the end address, which is
controlled by the synchronisation pulses in x- and y direction.
The readout itself is straightforward. Line by line is selected by
means of a sync-pulse and by means of a Clock_y signal. Once
a new line selected, it takes a while (row blanking time) before
the information of that line is stable. After this row blanking time
the data is multiplexed in blocks of 16 to the output amplifiers. A
sync-pulse and a clock pulse in the x-direction do this multi-
plexing.
Figure 14
selection signals of the pixels, which are sequentially active,
starting by the sync pulse. The next line is selected on the rising
edge of Clock_y. It is important that the Sync_y pulse covers 1
rising edge of the Clock_y signal. Otherwise the synchronization
will not work properly.
shows the y-address timing. The top curves are the
CYIL1SM1300AA
Figure 12
shows the timing
Page 14 of 29
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