AK4621 AKM [Asahi Kasei Microsystems], AK4621 Datasheet
AK4621
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AK4621 Summary of contents
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... The AK4621 is a high performance 24-bit CODEC that supports up to 192kHz recording and playback. The on-board analog-to-digital converter has a high dynamic range due to AKM’s Enhanced Dual-Bit architecture. The DAC utilizes AKM’s Advanced Multi-Bit architecture that achieves low out-of-band noise and high jitter tolerance through the use of Switched Capacitor Filter (SCF) technology ...
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... AOUTL+ AOUTL- AOUTR+ AOUTR- MS1258-E-01 VSS1 VCOM VREF HPF ADC OVF DATT SMUTE DAC SDFIL DEM0 Figure 1. Block Diagram - 2 - DVDD TVDD VSS2 PDN LRCK BICK Audio SDTO Interface SDTI MCLK DFS0 Control P/S Register I/F CSN/ CCLK/ CDTI/ DIF CKS1 CKS0 [AK4621] 2011/01 ...
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... AKD4621 ■ Pin Layout VCOM AINR+ AINR- AINL+ AINL- VREF VSS1 AVDD P/S MCLK LRCK BICK SDTO SDTI OVFR/DZFR MS1258-E-01 −10 ∼ +70°C 30pin VSOP (0.65mm pitch) Evaluation board for AK4621 Top View [AK4621] AOUTR+ 30 ...
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... IATTL4 IATTR7 IATTR6 IATTR5 IATTR4 DATTL6 DATTL5 DATTL4 DATTR6 DATTR5 DATTR4 0 0 EXTE These bits were added in the AK4621. These bits were deleted in the AK4621 AK4621 ← Differential - - 102dB 115dB Sharp Roll-off Sharp Roll-off 100dB 39/fs 100dB (-1dBFS) ← Sharp Roll-off ...
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... Lch Positive Analog Output Pin 29 AOUTR- O Rch Negative Analog Output Pin 30 AOUTR+ O Rch Positive Analog Output Pin Note 1. All digital input pins (P/S, MCLK, LRCK, BICK, SDTI, CDTI/CKS0, CCLK/CKS1, CSN/DIF, DFS0, PDN, DEM0 and SDFIL) must not be left floating. MS1258-E-01 PIN/FUNCTION Function - 5 - [AK4621] 2011/01 ...
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... These pins must be open. These pins must be open. ABSOLUTE MAXIMUM RATINGS Symbol AVDD DVDD TVDD IIN (Note 4) VINA (Note 5) VIND Ta Tstg Symbol min AVDD 4.75 DVDD 3.0 TVDD DVDD VREF 3 [AK4621] Setting min max Units -0.3 6.0 -0.3 6.0 -0.3 6.0 ± -0.3 AVDD+0.3 -0.3 TVDD+0.3 -10 70 -65 150 typ max Units 5.0 5.25 3 ...
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... Note 10) - (Note 10, Note 11) 107 90 - (Note 12) - ±2.6 (Note 13) - (Note 14 [AK4621] typ max Units - 24 Bits ±2.82 ±3.02 Vpp 13 - kΩ kΩ kΩ 102 - 101 - 101 - 115 - dB 115 - dB ...
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... AVDD DVDD+TVDD (fs=48kHz) (fs=96kHz) (fs=192kHz) Power-down mode (PDN pin = “L”) AVDD DVDD+TVDD Note 15. All digital input pins are held TVDD or VSS2. MS1258-E-01 min typ - (Note 15 [AK4621] max Units μA 100 μA 100 2011/01 ...
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... MS1258-E-01 Symbol min 16 100 17 Δ Symbol min 16 100 17 Δ [AK4621] typ max Units - 21.8 kHz 22.0 - kHz 22.3 - kHz 24.0 - kHz - - kHz ±0.005 - 1/fs μ 1 6 typ max Units - 43.7 kHz 44.1 - kHz 44.5 - kHz 48 ...
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... ADC output register for ADC. If the signal is outputted to the SDTO pin, group delay is increased 0.5/fs from the above value. MS1258-E-01 Symbol min 16) SB 106 100 17 Δ [AK4621] typ max Units - 87.0 kHz 88.2 - kHz 89.0 - kHz 96.0 - kHz - - kHz ±0. ...
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... Δ Symbol min 16 Δ Symbol min 16) SB 141 17 Δ [AK4621] typ max Units - 21.7 kHz 22.1 - kHz 23.8 - kHz 24.4 - kHz - - kHz ±0. 1/fs μs ±0. typ max Units - 43.3 kHz 44.2 - kHz 47.6 - kHz 48.9 - kHz - - kHz ± ...
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... MS1258-E-01 Symbol min 18 Symbol min 18 symbol min 18) SB 105 19 [AK4621] typ max Units - 21.8 kHz 24.0 - kHz - - kHz - ±0. 1/fs ± 0 typ max Units - 43.5 kHz 48.0 - kHz - - kHz - ±0. 1/fs ± 0 typ ...
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... MS1258-E-01 Symbol min 18 Symbol min 18 Symbol min 18) SB 170 19 [AK4621] typ max Units - 8.9 kHz 19.8 - kHz - - kHz - ±0. 1/fs +0/- typ max Units - 17.7 kHz 39.5 - kHz - - kHz - ±0. 1/fs +0/- typ ...
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... MS1258-E-01 Symbol min 18 Symbol min 18 symbol min 18) SB 104 19 [AK4621] typ max Units - 21.8 kHz 24.0 - kHz - - kHz - ±0. 1/fs ± 0 typ max Units - 43.5 kHz 48.0 - kHz - - kHz - ±0. 1/fs ± 0 typ ...
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... BICK “↓” to SDTO SDTI Hold Time SDTI Setup Time Note 20. When the normal/double/quad speed modes are switched, the AK4621 must be reset by the PDN pin or RSTN bit. Note 21. BICK rising edge must not occur at the same time as LRCK edge. MS1258-E-01 ...
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... CCLK “↑” to CSN “↑” Reset Timing PDN Pulse Width RSTAD “↑” to SDTO Valid Note 22. The AK4621 can be reset by bringing the PDN pin “L”. Note 23. These cycles are the number of LRCK rising from RSTAD bit. MS1258-E-01 Symbol ...
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... LRCK BICK LRCK BICK SDTO SDTI MS1258-E-01 1/fCLK tCLKH tCLKL 1/fs tBCK tBCKH tBCKL Figure 2. Clock Timing tBLR tLRB tLRS tSDS tSDH Figure 3. Audio Interface Timing - 17 - [AK4621] VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL tBSD 50%TVDD VIH VIL 2011/01 ...
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... C1 C0 R/W Figure 4. WRITE Command Input Timing tCSH Figure 5. WRITE Data Input Timing tPD Figure 6. Power Down & Reset Timing - 18 - [AK4621] VIH VIL VIH VIL VIH A4 VIL tCSW VIH VIL tCSS VIH VIL VIH VIL VIL ...
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... The AK4621 requires MCLK, BICK and LRCK external clocks. MCLK must be synchronized with LRCK but the phase is not critical. The AK4621 is automatically placed in power-down state when MCLK is stopped more than 9.38µs during a normal operation (PDN pin =“H”), then the digital output becomes “0” data and the analog output becomes Hi-Z. When MCLK and LRCK are input again, the AK4621 exit power-down state and starts the operation. After exiting system reset (PDN pin =“ ...
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... N/A 36.864MHz 384fs fs=192kHz 24.576MHz 49.152MHz 36.864MHz - 20 - Sampling Rate 32kHz-54kHz 54kHz-108kHz MCLK Double Speed (DFS0 pin = “H”) N/A 256fs Auto Setting Mode (*) 512fs Table 6.) (N/A: Not Available) Sampling Rate 32kHz-54kHz 54kHz-108kHz 108kHz-216kHz fs=88.2kHz fs=96kHz N/A N/A 22.5792MHz 24.576MHz 45.1584MHz 49.152MHz N/A N/A 33.8688MHz 36.864MHz [AK4621] 2011/01 ...
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... I S L/H ≥ 48fs H/L LRCK BICK ≥ 48fs H/L 2 ≥ 48fs S L Rch Data Rch Data [AK4621] (default 2011/01 ...
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... Don’t Care Rch Data Rch Data Rch Data [AK4621 Don’t Care 2011/01 ...
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... Output Volume The AK4621 includes channel independent digital output volumes (DATT) with 256 levels and extension digital output volumes (EATT) with 16 levels at linear steps including MUTE. When EXTE bit = “1”, the extension digital output volumes are enabled. These volumes are in front of the DAC. If the extension digital output volumes are disabled, the volumes can attenuate the input data from 0dB to − ...
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... The digital high pass filter cut-off frequency scales with the sampling rate (fs). In parallel mode, the HPF is always enabled. In serial mode, the HPF can control each channel by HPLN/HPRN bits. MS1258-E-01 EATTL3-0 bits GAIN(dB) EATTR3-0 bits 20 log 10 (DATT_DATA / 255 log 10 (EATT_DATA / 4095 Table 13. Output Digital Volume Formula - 24 - [AK4621] 2011/01 ...
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... Digital Filter The AK4621 has two kinds of Digital Filter for ADC and three kinds of Digital Filter for DAC. The outputs of ADC and DAC can be controlled by using the SDFIL pin or SDAD/SDDA/SLOW bits. SDFIL pin L Short Delay Sharp Roll Off Filter H Table 14. Digital Filter Selection in Parallel Mode ...
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... The DZF pin immediately returns to “L” if input data are not zero after going to “H”. MS1258-E-01 (Table ( (2) (4) 8192/fs (Table 10). For example, in Normal Speed Mode, if the EATT is disabled, this Figure 12. Soft Mute and Zero Detection - 26 - [AK4621] 10) from the current ATT level. When (1) ( (2) 2011/01 ...
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... Power Down & Reset The ADC and DAC of AK4621 are placed in power-down mode by bringing the PDN pin = “L”. Each digital filter is also reset at the same time. The internal register values are initialized by bringing the PDN pin to “L”. This reset must always be done after power-up. As both control registers of the ADC and the DAC go to the reset state (RSTAD bit = RSTDA bit = “ ...
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... Click noise occurs at the rising/falling edge of PDN. (6) Mute the analog output externally if the click noise (5) influences system application. (7) When MCLK is stopped more than 9.38µs, the AK4621 becomes power down mode. Then ADC output is “0” data and DAC output is floating (Hi-Z). ...
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... Parallel mode R C1-C0: Chip Address (Fixed to “10”) R/W: READ/WRITE (Fixed to “1”:WRITE) A4-A0: Register Address D7-D0: Control data Figure 15. Control I/F Timing - 29 - Serial mode [AK4621] 2011/01 ...
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... Control Register Setup Sequence When the PDN pin goes “L” to “H” upon power-up etc., the AK4621 will be ready for normal operation by the sequence below. In this case, all control registers are set to default values and the AK4621 is in the reset state. ...
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... DZF goes “H” at Zero Detection (default) 1: DZF goes “L” at Zero Detection SLOW: DAC Slow Roll Off Filter Enable Default: Disable MS1258-E- SLOW DZFB ZOE ZOS (Table 16) (Table 16 [AK4621 SDDA PWVR PWAD PWDA 2011/01 ...
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... Default: 24bit MSB justified for both ADC and DAC MS1258-E- SDAD 15) (Table DIF2 DIF1 DIF0 CMODE (Table 1) (Table 2) (Table [AK4621 RSTAD RSTDA CKS1 CKS0 DFS1 DFS0 2011/01 ...
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... EXTE DEM1 DATTL3 DATTL2 DATTL1 DATTR3 DATTR2 DATTR1 Table 13 EATTL3 EATTL2 EATTL1 0 EATTR3 EATTR2 EATTR1 (Table 12, Table 13) [AK4621] D0 DEM0 1 D0 DATTL0 DATTR0 1 D0 EATTL0 EATTR0 1 2011/01 ...
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... VSS1 TVDD AK4621 AVDD SDFIL P/S DEM0 PDN MCLK LRCK DFS0 BICK CSN/DIF SDTO CCLK/CKS1 SDTI CDTI/CKS0 OVFR/DZFR OVFL/DZFL Figure 16. Typical Connection Diagram - 34 - [AK4621] 30 Rch Rch Out LPF 29 28 Lch Lch Out LPF 27 26 3.0 ∼ 3.6V 25 Digital Supply 0.1u 0.1u DVDD ∼ 5.25V 24 Digital Supply 23 ...
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... DVDD and TVDD must be distributed separately from the point with low impedance of regulator etc. The power up sequence is not critical among AVDD, DVDD and TVDD. VSS1 and VSS2 must be connected to one analog ground plane. Decoupling capacitors must be as near to the AK4621 as possible, with the small value ceramic capacitor being the nearest. ...
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... Analog Inputs The AK4621 can accept input voltages from VSS1 to AVDD. The input signal range scales with the VREF voltage and is nominally 2.82Vpp (VREF = 5V), centered around the internal common voltage (about VA/2). buffer circuit example. This is a fully differential input buffer circuit with an inverted amplifier (gain: −10dB). The capacitor of 10nF between AINL+/− ...
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... AOUT+ Figure 19. External LPF Circuit Example 1 (fc = 136kHz, Q=0.694) Table 19. Frequency Response of External LPF Circuit Example 1 MS1258-E-01 4.7k 4.7k 200 2.2n 200 4.7k 4.7k 330p Frequency Response Gain −0.01dB 20kHz −0.06dB 40kHz −0.59dB 80kHz - 37 - [AK4621] Figure 20 shows an 330p +Vop Analog Out -Vop 2011/01 ...
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... Figure 20. External LPF Circuit Example Stage 2 182kHz 284kHz 0.637 +3.9dB -0.88dB 20kHz -0.025 -0.021 40kHz -0.106 -0.085 80kHz -0.517 -0.331 - 38 - +15 -15 0.1u 560 + 1.0n 100 620 620 1.0n NJM5534D + 10u 0.1u Stage Total - - - +3.02dB -0.046dB -0.191dB -0.848dB [AK4621] 10u Lch 2011/01 ...
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... N OTE: Dimension "* " does not include mold flash. ■ Package & Lead frame material Package molding compound: Epoxy Resin, Halogen (bromine and chlorine) free Lead frame material: Cu Alloy Lead frame surface treatment: Solder (Pb free) plate MS1258-E-01 PACKAGE *9.7±0 0.65 0. [AK4621] 1. 5MAX A +0.06 0.17 -0.05 D etail A 0° ~ 8° 2011/01 ...
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... MS1258-E-01 MARKING AKM AK4621EF XXXXYYYYZ YYYY: Date code XXXX, Z: Internal control code - 40 - [AK4621] 2011/01 ...
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... MS1258-E-01 REVISION HISTORY Page/Line Contents Digital filter names were changed. IMPORTANT NOTICE , and AKM assumes no responsibility for such use, except for the use Note2 [AK4621] in any safety, life support, or Note1) 2011/01 ...