AK4635 AKM [Asahi Kasei Microsystems], AK4635 Datasheet - Page 61

• Manufacturer Part Number: AK4635
• Description: 16-Bit Mono CODEC with ALC & MIC/SPK/Video-AMP
• Manufacturer: AKM [Asahi Kasei Microsystems]

(2) I
The AK4635 supports the fast-mode I
to (DVDD+0.3)V or less voltage.
(2)-1. WRITE Operations
Figure 54
HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition
START condition, a slave address is sent. This address is 7 bits long followed by the eighth bit that is a data direction bit
(R/W). The most significant seven bits of the slave address are fixed as “0010010”
matches that of the AK4635, the AK4635 generates an acknowledge and the operation is executed. The master must
generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse
(Figure
operation is to be executed.
The second byte consists of the control register address of the AK4635. The format is MSB first, and those most
significant 1-bits are fixed to zeros
first, 8bits
terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is
HIGH defines a STOP condition
The AK4635 can perform more than one byte write operation per sequence. After receipt of the third byte the AK4635
generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the
write cycle after the first data byte is transferred. After receiving each data packet the internal 6-bit address counter is
incremented by one, and the next data is automatically taken into the next address. If the address exceeds 4FH prior to
generating a stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten.
The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data
line can only change when the clock signal on the SCL line is LOW
conditions.
Rev. 0.6
2
C-bus Control Mode (I2C pin = “H”)
61). A R/W bit value of “1” indicates that the read operation is to be executed. A “0” indicates that the write
shows the data transfer sequence for the I
(Figure
SDA
57). The AK4635 generates an acknowledge after each byte is received. A data transfer is always
S
T
A
R
T
S
Slave
Address
D7
0
0
R/W="0"
Figure 54. Data Transfer Sequence at the I
A
C
K
(Figure
A6
D6
0
(Figure
Figure 57. Byte Structure after the second byte
Sub
Address(n)
2
C-bus (max: 400kHz). Pull-up resistors at SDA and SCL pins should be connected
60).
56). The data after the second byte contains control data. The format is MSB
A5
D5
1
Figure 56. The Second Byte
Figure 55. The First Byte
C
A
K
2
C-bus mode. All commands are preceded by a START condition. A
Data(n)
A4
D4
0
- 61 -
A
C
K
A3
D3
0
(Figure
Data(n+1)
2
A2
D2
C-Bus Mode
1
62) except for the START and STOP
C
A
K
(Figure
A1
D1
0
A
C
K
55). If the slave address
Data(n+x)
(Figure
R/W
A0
D0
60). After the
C
A
K
S
T
O
P
P
[AK4635]
2007/10