AK4122A AKM [Asahi Kasei Microsystems], AK4122A Datasheet - Page 10

• Manufacturer Part Number: AK4122A
• Description: 24-Bit 96kHz SRC with DIR
• Manufacturer: AKM [Asahi Kasei Microsystems]

(Ta=25°C; AVDD=DVDD=3.0 ∼ 3.6V; C
Parameter
Master Clock Timing
LRCK for Input data (LRCK1, LRCK2)
LRCK for Output data (LRCK, LRCK2)
S/PDIF Clock Recover Frequency
Audio Interface Timing
Note 10. Min value is 8kHz at BYPASS mode.
Note 11. BICK1 rising edge must not occur at the same time as LRCK1 edge.
MS1076-E-01
Input for PORT1
BICK1 Period
BICK1 Pulse Width Low
LRCK1 Edge to BICK1 “↑”
BICK1 “↑” to LRCK1 Edge
SDTI Hold Time from BICK1 “↑”
SDTI Setup Time to BICK1 “↑”
Input for PORT2 (Slave mode)
BICK2 Period
BICK2 Pulse Width Low
LRCK2 Edge to BICK2 “↑”
BICK2 “↑” to LRCK2 Edge
SDTIO Hold Time from BICK2 “↑”
SDTIO Setup Time to BICK2 “↑”
Output for PORT2 (Slave mode)
BICK2 Period
BICK2 Pulse Width Low
LRCK2 Edge to BICK2 “↑”
BICK2 “↑” to LRCK2 Edge
LRCK2 to SDTIO (MSB) (Except I
BICK2 “↓” to SDTIO
Frequency
Pulse Width Low
Pulse Width High
Frequency
Duty Cycle
Frequency
Duty Cycle
BICK2 rising edge must not occur at the same time as LRCK2 edge.
Pulse Width High
Pulse Width High
Pulse Width High
Master Mode
Slave Mode
SWITCHING CHARACTERISTICS
(Note
(Note
(Note
(Note
(Note
(Note
(Note
2
L
S mode)
=20pF)
11)
11)
11)
11)
11)
11)
10)
Symbol
tCLKH
tBCKH
tBCKH
tBCKH
tCLKL
tBCKL
tBCKL
tBCKL
fCLK
tBCK
tSDH
tBCK
tSDH
tBCK
tLRB
tBLR
tLRB
tBLR
tLRB
tBLR
tBSD
fPLL
tSDS
tSDS
tLRS
Duty
Duty
Duty
- 10 -
fs
fs
0.4/fCLK
0.4/fCLK
1/64fs
1/64fs
1/64fs
8.192
min
48
32
48
32
65
65
30
30
30
30
65
65
30
30
30
30
65
65
30
30
8
typ
50
50
50
36.864
max
96
52
96
52
96
30
30
[AK4122A]
Units
2010/05
MHz
kHz
kHz
kHz
ns
ns
%
%
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns