AK4122A AKM [Asahi Kasei Microsystems], AK4122A Datasheet - Page 24

• Manufacturer Part Number: AK4122A
• Description: 24-Bit 96kHz SRC with DIR
• Manufacturer: AKM [Asahi Kasei Microsystems]

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Bringing the PDN pin = “L” sets the AK4122A in power-down mode and initializes digital filters. When the PDN pin =
“L”, the SDTO output is “L”. The AK4122A should be reset once by bringing the PDN pin = “L” upon power-up. The
SDTO becomes valid in less than 100ms from the rising edge of PDN after a reset release by clock supply. Until the
SDTO becomes valid, it outputs “L”. After the rising of PDN pin, the SDTIO pin is an input pin.
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A clock change sequence is shown in
changed. The SDTO data is placed “0” during the reset. Within 100ms, the SDTO outputs normal data after the reset.
When the frequency transition occurs gradually without phase change or when the output clock is changed while fso/fsi >
4, the output data may have large distortion for several seconds. A reset should be made by bringing the PDN pin = “L” or
PWN bit = “0” to obtain normal data within 100ms when clocks are changed.
Note 16. The data on SDTO may cause a clicking noise. To prevent this, set SDTI or SDTIO to “0” from GD before the
Note 17. The data on SDTO may cause a clicking noise. To prevent this, set SDTI to “0” for 1024/fso+100ms or more
Note 18. The data on SDTO may cause a clicking noise. To prevent this, set SDTI to “0” for 1024/fso+100ms or more
MS1076-E-01
System Reset
Sequence of Changing Clocks
External clocks
(internal state)
SDTO
PDN
(input / output port)
PDN pin changes to “L”, which will cause the data on SDTO to remain “0”. SMUTE can also remove this
clicking noise.
from the timing when the PDN pin changes to “H” while the SMUTE pin = “H”.
from the timing when the PDN pin changes to “H” while the SMUTE pin = “H”.
External clocks
(Input port
PDN pin
(Internal state)
SDTIO/SDTO
SMUTE
Att.Level
or Output port)
(recommended)
-
Power-down
0dB
∞
don’t care
dB
Normal operation
Normal data
Figure 14.
Figure 14. Sequence of Changing Clocks
Clocks 1
1024/fso
PLL locktime & fs detection
Figure 13. System Reset
< 100msec
An internal reset is executed when the input or the output clocks are
“0” data
Power-down
Don’t care
Note16
- 24 -
(stable)
PLL lock &
fs detection
< 100ms
Note17
Clocks 2
normal operation
normal data
1024/fso
Normal operation
Normal data
Power-down
don’t care
“0” data
[AK4122A]
2010/05