AK4160 AKM [Asahi Kasei Microsystems], AK4160 Datasheet - Page 14

• Manufacturer Part Number: AK4160
• Description: 16-channel Capacitive Touch Sensor IC
• Manufacturer: AKM [Asahi Kasei Microsystems]

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The AK4160 is controlled by a microprocessor via I
Note that the AK4160 operates in those two modes and does not support a High speed mode I
The AK4160 can operate as a slave device on the I
voltage down to 1.71V in order to connect a low voltage microprocessor.
1. WRITE Operations
Figure 10
HIGH to LOW transition on the SDA line while SCL is HIGH indicates START condition
condition, a slave address is sent. This address is 7 bits long followed by the eighth bit that is a data direction bit (R/W).
The most significant five bits of the slave address are fixed as “10100”. The next bits is AD1 and AD0 (device address bit).
These bits identify the specific device on the bus. The hard-wired input pin (AD0, AD1 pin) set this device address bit
(Figure
executed. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the
acknowledge clock pulse
indicates that the write operation is to be executed.
The second byte consists of the control register address of the AK4160. The format is MSB first, and those most
significant two bits are fixed to zeros
first, 8bits
terminated by STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is HIGH
defines STOP condition
The AK4160 can perform more than one byte write operation per sequence. After receipt of the third byte the AK4160
generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the
write cycle after the first data byte is transferred. After receiving each data packet the internal 6-bit address counter is
incremented by one, and the next data is automatically taken into the next address. If the address exceeds “9FH” prior to
generating stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten.
The data on the SDA line must remain stable during the HIGH period of the clock. HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is LOW
MS1313-E-01
Digital I/F
11). If the slave address matches that of the AK4160, the AK4160 generates an acknowledge and the operation is
shows the data transfer sequence for the I
(Figure
13). The AK4160 generates an acknowledge after each byte is received. A data transfer is always
(Figure
(Figure
14).
Touch Switch
15). R/W bit value of “1” indicates that the read operation is to be executed. “0”
(Figure
12). The data after the second byte contains control data. The format is MSB
Figure 9. Digital I/F
2
C bus network. The digital I/O of AK4160 operates off of supply
2
2
C-bus mode. All commands are preceded by START condition. A
C bus supporting standard mode (100kHz) and fast mode (400kHz).
AK4160
- 14 -
VDD=1.71V ~ 3.6V
(Figure
AD0,AD1
“L” or “H”
IRQ0N/IRQ1N/IRQ2N
16) except for the START and STOP conditions.
SDA
SCL
Rp
Rp
Processor
Controller
I
(Figure
Micro-
2
C bus
(µP)
2
C-bus system (3.4MHz).
14). After the START
[AK4160]
2011/11