AK4687 AKM [Asahi Kasei Microsystems], AK4687 Datasheet - Page 22

• Manufacturer Part Number: AK4687
• Description: Asynchronous Stereo CODEC with Capless Stereo Selector
• Manufacturer: AKM [Asahi Kasei Microsystems]

■
The ADC and DAC blocks of the AK4687 are placed in power-down mode by bringing the PDN1 pin and PDN2 pin to
“L” respectively and both digital filters are reset at the same time. The PDN1 pin = PDN2 pin =“L” also reset the control
registers to their default values. In power-down mode, the DAC outputs 0V and the SDTO pin goes to “L”. This reset must
always be executed after power-up.
In master mode, the ADC starts operation on the rising edge of MLCK1 after power-down mode is released by a status
change of the PDN1 pin from “L” to “H”. In slave mode, when power down mode is released by a status change of the
PDN1 pin from “L” to “H”, the ADC starts operation on the rising edge of LRCK1 after MLCK1, LRCK1 and BICK1 are
input.
The DAC starts operation on the rising of the LRCK2, after power-down mode is released by a status change of the PDN2
pin from “L” to “H”, and MCLK2, LRCK2 and BICK2 are input.
The analog initialization cycle of ADC starts after exiting the power-down mode. Therefore, the output data, SDTO
becomes available after 2640 cycles of LRCK1 clock. In case of the DAC, an analog initialization cycle starts after exiting
the power-down mode. The analog outputs are 0V during the initialization.
sequence.
The ADC and DAC can be powered-down individually by PWAD and PWDA bits. Register values are not initialized by
these bits. When PWAD bit = “0”, the ADC output goes to “L”. When PWDA bit = “0”, the DAC output goes to 0V. As
some click noise occurs, the analog output should be muted externally if the click noise influences system application.
Clock In
MCLK1,LRCK1,BICK1
MCLK2,LRCK2,BICK2
MS1307-E-00
DAC Internal
DAC In
DAC Out
CVEE pin
VREF1/2 pin
ADC Internal
ADC In
ADC Out
PDN1 pin =
PDN2 pin
Power
(Digital)
(Internal Status)
Power ON/OFF Sequence
(Analog)
(Digital)
State
State
Don’t care
0V
0V
(1)
“0”data
“0”data
(2)
(9)
(6)
Figure 10. Power-up/down sequence example
(8)
timeB
(4)
Init Cycle
timeA
- 22 -
(3)
CVEE
80% AVDD2
Normal Operation
(5)
GD
Normal Operation
GD
Figure 10
(5)
shows power-down and power-up
GD
GD
Power-down
Power-down
(7)
“0”data
“0”data
[AK4687]
Don’t care
0V
2011/05