AK4186 AKM [Asahi Kasei Microsystems], AK4186 Datasheet - Page 11

• Manufacturer Part Number: AK4186
• Description: Low Power Touch Screen Controller with I2C Interface
• Manufacturer: AKM [Asahi Kasei Microsystems]

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The AK4186 is controlled by a microprocessor via I
(400kHz). Note that the AK4186 operates in those two modes and does not support a High speed mode I
(3.4MHz). The AK4186 can operate as a slave device on the I
voltage down to 1.6V in order to connect a low voltage microprocessor.
1. WRITE Operations
Figure 7
HIGH to LOW transition on the SDA line while SCL is HIGH indicates START condition
START condition, a slave address is sent. This address is 6 bits long followed by the eighth bit that is a data direction
bit (R/W). The most significant five bits of the slave address are fixed as “100100”. The next bit is CAD0 (device
address bit). This bit identify the specific device on the bus. The hard-wired input pin (CAD0 pin) set this device
address bit
operation is executed. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH)
during the acknowledge clock pulse
“0” indicates that the write operation is to be executed.
The second byte consists of the control register address of the AK4186. The format is MSB first, and those most
significant two bits are fixed to zeros
MSB first, 8bits
always terminated by STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL
is HIGH defines STOP condition
The AK4186 can perform more than one byte write operation per sequence. After receipt of the third byte the AK4186
generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating
the write cycle after the first data byte is transferred. After receiving each data packet the internal 6-bit address counter
is incremented by one, and the next data is automatically taken into the next address. If the address exceeds 1FH prior to
generating stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten.
The data on the SDA line must remain stable during the HIGH period of the clock. HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is LOW
MS1068-E-04
Digital I/F
shows the data transfer sequence for the I
(Figure
(Figure
8). If the slave address matches that of the AK4186, the AK4186 generates an acknowledge and the
4/5-wire touch panel
10). The AK4186 generates an acknowledge after each byte is received. A data transfer is
(Figure
(Figure
(Figure
11).
12). R/W bit value of “1” indicates that the read operation is to be executed.
9). The data after the second byte contains control data. The format is
Figure 6. Digital I/F
2
C-bus mode. All commands are preceded by START condition. A
2
C bus and supports standard mode (100kHz) and fast mode
AK4186
- 11 -
2
C bus network. The AK4186 operates off of supply
VDD=1.6V ~ 3.6V
(Figure
CAD0
“L” or “H”
13) except for the START and STOP conditions.
SDA
SCL
PENIRQN
Rp
Rp
Processor
Controller
I
Micro-
2
(Figure
C bus
11). After the
2
C-bus system
[AK4186]
2011/03