AK4186 AKM [Asahi Kasei Microsystems], AK4186 Datasheet - Page 22

• Manufacturer Part Number: AK4186
• Description: Low Power Touch Screen Controller with I2C Interface
• Manufacturer: AKM [Asahi Kasei Microsystems]

Touch Screen
PENIRQN
■
(1) Setup Sequence
In case of the single measurement mode, this touch panel configuration register sets the measurement mode of the
AK4186. Touch screen driver switches are turned ON at Driver ON mode (PD0 bit = “1”) on the rising edge of the 27th
SCL. It is possible to have longer tracking time even if the source of analog input impedance is high, because the actual
sampling is executed at the read operation. If a current measurement is made by the same setting of PD0 bit as the last
time, the setup sequence is unnecessary.
(2) Single Measurement Sequence
When the master send a READ command after sending a control register address for a measurement channel by a
WRITE operation, the AK4186 starts A/D conversion in single mode. This A/D conversion is synchronized with the
internal clock. The internal oscillator of the AK4186 is automatically powered up on the falling edge of 25th SCL after
writing the register address, and the AK4186 samples the analog input and completes A/D conversion after the rising
edge of 26th SCL. The master receives the first byte of serial data (D11-D4, MSB first), and generates an acknowledge.
Then the master receives the second byte of serial data (D3-D0, followed by four 0 bits). When the master continuously
reads ADC data, the master repeats read operation after generating an acknowledge. If the master does not generate an
acknowledge but generates stop condition instead, the AK4186 ceases continuous operation.
MS1068-E-04
Driver SW
OSCLK
SDA
SCL
Touch Screen Controller Control Sequence (Single Mode)
SDA
Touch Screen
Driver SW
SCL
START
PD0=“1”
PD0=“0”
PD0=“0”
START
0
PD0=0
PD0=1
0
1
1
1
0
2
Slave Address Byte
1
3
0
0
“H”
“Off”
4
2
1
5
0
Slave Address Byte
0
3
6
0
CAD
7
1
0
4
R/ W
8
0
AK4186
ACK
0
Figure 28. Single Measurement operation and Driver SW timing
9
5
0
10 11 12 13 14 15 16 17 18
0
6
Sub Address Byte
Register Addr = 20H~28H
CAD0
Figure 27. Setup operation and Driver SW timing
ENABLE
7
R/ W
0
8
AK4186
ACK
0
9
10
AK4186
ACK
11
START
Register Addr = 01H
Sub Address Byte
12
19 20 21 22 23 24 25 26 27 28 29 30 31 32
1
13
0
Slave Address Byte
- 22 -
0
14
1
0
15
Sampling
0
CAD
16
0
R/ W
1
AK4186
17
ACK
AK4186
0
ACK
D11
0
18
D10 D9
AD conv.
PANEL
Data Byte (MSB)
19
D8
0
20
D7
SLEEP
33 34 35 36 37 38 39
D6
1
21
D5
SLEEP
Data Byte
0
D4
22
Master
ACK
“L”
0
0
23
D3
D2
0
24
Data Byte (LSB)
D1
0
D0
25
40 41 42 43 44 45 46
PD0
0
26
Sampling
AK4186
0
ACK
0
0
27
Master
[AK4186]
ACK
0
STOP
1
2011/03
STOP
ENABLE
AD conv.