SPT9689BCU CADEKA [Cadeka Microcircuits LLC.], SPT9689BCU Datasheet - Page 3
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SPT9689BCU
Manufacturer Part Number
SPT9689BCU
Description
DUAL ULTRAFAST VOLTAGE COMPARATOR
Manufacturer
CADEKA [Cadeka Microcircuits LLC.]
Datasheet
1.SPT9689BCU.pdf
(8 pages)
TEST LEVEL CODES
All electrical characteristics are subject to the
following conditions:
All parameters having min/max specifications
are guaranteed. The Test Level column indi-
cates the specific device testing actually per-
formed during production and Quality Assur-
ance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.
TIMING INFORMATION
The timing diagram for the comparator is shown in figure
1. If LE is high and LE low in the SPT9689, the comparator
tracks the input difference voltage. When LE is driven low
and LE high, the comparator outputs are latched into their
existing logic states.
The leading edge of the input signal (which consists of a
20 mV overdrive voltage) changes the comparator output
after a time of t
be maintained for a time t
ing edge and LE rising edge and held for time t
Figure 1 – Timing Diagram
pdL
or t
pdH
S
(Q or Q). The input signal must
(set-up time) before the LE fall-
LEVEL
III
IV
VI
H
II
V
I
after the
TEST PROCEDURE
100% production tested at the specified temperature.
100% production tested at T
specified temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design and characteri-
zation data.
Parameter is a typical value for information purposes only.
100% production tested at T
over specified temperature range.
3
falling edge for the comparator to accept data. After t
output ignores the input status until the latch is strobed
again. A minimum latch pulse width of t
strobe operation, and the output transitions occur after a
time of t
The set-up and hold times are a measure of the time
required for an input signal to propagate through the first
stage of the comparator to reach the latching circuitry.
Input signals occurring before t
those occurring after t
between t
pLOH
S
and t
or t
pLOL
H
may not be detected.
A
A
.
= +25 °C, and sample tested at the
= +25 °C. Parameter is guaranteed
H
will not be detected. Changes
S
will be detected and held;
pL
is needed for
SPT9689
H
2/20/01
, the