82V3352EDG IDT [Integrated Device Technology], 82V3352EDG Datasheet - Page 40
82V3352EDG
Manufacturer Part Number
82V3352EDG
Description
SYNCHRONOUS ETHERNET WAN PLL
Manufacturer
IDT [Integrated Device Technology]
Datasheet
1.82V3352EDG.pdf
(125 pages)
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Table 27: Read Timing Characteristics in Serial Mode
Table 28: Write Timing Characteristics in Serial Mode
Microprocessor Interface
IDT82V3352
Symbol
Symbol
t
t
t
t
t
t
t
pw1
pw2
t
t
t
t
t
t
t
t
su1
su2
t
out
pw1
pw2
t
t
T
d1
d2
h1
h2
su1
su2
t
TI
t
out
in
T
h1
h2
in
TI
SCLK
CS
SDO
SDI
Time between consecutive Read-Read or Read-Write accesses
Time between consecutive Write-Write or Write-Read accesses
CS rising edge to SDO high impedance delay time
Valid CS after valid SCLK hold time (CLKE = 0/1)
t
su2
t
su1
R/ W
Valid SDI after valid SCLK hold time
Valid SDI after valid SCLK hold time
Valid CS after valid SCLK hold time
Valid SCLK to valid data delay time
( CS rising edge to CS falling edge)
Valid SDI to valid SCLK setup time
( CS rising edge to CS falling edge)
One cycle time of the master clock
Valid SDI to valid SCLK setup time
One cycle time of the master clock
Valid CS to valid SCLK setup time
Valid CS to valid SCLK setup time
t
h1
SCLK pulse width high
SCLK pulse width high
A0
SCLK pulse width low
SCLK pulse width low
Delay of output pad
Delay of output pad
Delay of input pad
Delay of input pad
Parameter
Parameter
A1
Figure 15. Serial Write Timing Diagram
A2
t
pw1
A3
t
pw2
A4
A5
40
A6
High-Z
D0
3.5T + 5
3.5T + 5
D1
3.5T
3.5T
Min
14
10
Min
4
6
5
14
10
4
6
5
D2
D3
12.86
D4
12.86
Typ
SYNCHRONOUS ETHERNET WAN PLL
Typ
10
10
5
5
5
5
D5
D6
D7
Max
Max
t
h2
March 23, 2009
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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