82V3352EDG IDT [Integrated Device Technology], 82V3352EDG Datasheet - Page 80

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82V3352EDG

Manufacturer Part Number
82V3352EDG
Description
SYNCHRONOUS ETHERNET WAN PLL
Manufacturer
IDT [Integrated Device Technology]
Datasheet
6.2.5
INPUT_VALID1_STS - Input Clocks Validity 1
INPUT_VALID2_STS - Input Clocks Validity 2
Programming Information
IDT82V3352
Address: 4AH
Type: Read
Default Value: XX0000XX
Address: 4BH
Type: Read
Default Value: XXXXXXX0
7 - 6
5 - 4
3 - 2
1 - 0
7 - 1
Bit
Bit
0
7
7
-
-
T0 DPLL INPUT CLOCK SELECTION REGISTERS
INn_CMOS
IN3_CMOS
INn_DIFF
Name
Name
-
-
-
6
6
-
-
Reserved.
This bit indicates the validity of the corresponding INn_DIFF. Here n is 2 or 1.
0: Invalid. (default)
1: Valid.
This bit indicates the validity of the corresponding INn_CMOS. Here n is 2 or 1.
0: Invalid. (default)
1: Valid.
Reserved.
Reserved.
This bit indicates the validity of the corresponding IN3_CMOS.
0: Invalid. (default)
1: Valid.
IN2_DIFF
5
5
-
IN1_DIFF
4
4
-
80
IN2_CMOS
3
3
-
Description
Description
IN1_CMOS
2
2
-
SYNCHRONOUS ETHERNET WAN PLL
1
1
-
-
March 23, 2009
IN3_CMOS
0
0
-

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