AM79C850KCW AMD [Advanced Micro Devices], AM79C850KCW Datasheet - Page 31

• Manufacturer Part Number: AM79C850KCW
• Description: SUPERNET-R 3
• Manufacturer: AMD [Advanced Micro Devices]

The two receive queues will have independent receive
FIFO’s. There will be two instructions to clear locks on
the two receive queues.
“Clear Receive Queue Lock” (instruction code 20h) will
be for RECV1 and the new instruction” Clear Receive2
Queue Lock “(instruction code 21h) will be for
RECV2 queue.
“Clear All Queue Locks” command would clear locks on
all queues. Clearing the queues would enable further
transfer of data received from the corresponding receive
FIFO. The received data present in the buffer memory
for each queue is indicated by the corresponding
RDATA pin. RECV1 data is indicated by RDATA1 and
RECV2 data is indicated by RDATA2. If the two receive
queue feature is not selected, RDATA1 would indicate
received data present in buffer memory. Read requests
will not be acknowledged when RDATA pins are
inactive. The status bits SRCOMP, SRBMT, SRABT,
SRBFL, SRCVOVR of status register 2 upper ST2U (bit
15–11) would be for RECV1 queue. The status bits
SRCOMP2, SRBMT2, SRABT2, SRBFL2, SRCVOVR2
of status register 3 upper ST3U (bit 15–11) would be for
RECV2 queue. The host interface to read the data
received in the second receive queue would use
HSREQ2–0 lines and the encoding would be
HSREQ[2:0] =001.
Address Bit Swapping
The SUPERNET 3 provides the necessary logic for
swapping the address fields within each frame between
FDDI and IEEE Canonical bit order. This involves a bit
reversal within each byte of the address field. This
feature is user selectable for transmit, receive or both,
however, once selected the bit swapping applies to all
queues. This is an useful feature for bridging Ethernet to
FDDI or for other higher level protocols. Bit 15 of the
FRSELREG, ENRCVADSWAP, enables the bit swap
on the receive queues. The FC field of the received
frame would decide whether the frame has long address
or
ENXMTADSWAP, enables the bit swap of the transmit
queues. The FC field of the frame to be transmitted will
decide whether the frame to be transmitted has long
address or short address. The CRC written into the
buffer memory will be the same as received. This logic
will not re-generate CRC after bit swapping on the
receive queues. The user can set MDREG2 bit 14,
STRPFCS, to strip receive FCS and prevent FCS being
short
address.
Bit
14
of
FRSELREG,
P R E L I M I N A R Y
SUPERNET 3
copied into the buffer memory. On the transmit side, the
address bits are swapped before the CRC generator,
and therefore, the transmitted CRC will be correct for
the bit swapped address.
Auto-Unlocking of Receive Queues
The buffer memory receive queue is locked out for any
further input when the receive buffer is full (RPRx =
WPRx after an increment of WPRx). The lock can be
cleared using the node processor commands “clear
receive queue lock (20h)” or “clear all queue locks
(3Fh)”. Once the lock has been cleared, the receive
buffer is available for further input. However, the node
processor has to clear the lock by using the CMDREG1
to enable reception of frames in the receive buffer. The
SUPERNET 3 provides an enhancement feature to
allow automatic unlocking of the receive queue based
on user-programmable host read count threshold. To
enable this feature, MENRQAUNLCK bit in Mode
Register 3 (MDREG3) needs to be set. If this bit is
cleared, which is the case at the time of reset, the
SUPERNET 3 behaves like FORMAC+ (i.e Upon buffer
full condition the receive queue is locked for further
input and needs a node processor command to clear
the lock).
If MENRQAUNLCK is enabled, the UNLCKDLY register
needs to be programmed with a 8 bit threshold value for
each receive queue. Upon receive buffer full condition,
the UNLCKDLY value times 4 will be loaded into a
counter. The counter will count down for every corre-
sponding host read receive acknowledge. After the
number of host read receive acknowledges exceeds the
user programmable count (UNLCKDLY) times 4, the
SUPERNET 3 would start receiving frames into the
corresponding receive buffer queue The SRBFLx bit in
ST2U and ST3U would indicate the status of the
corresponding receive buffer queue. If this bit is set it
indicates that the corresponding receive buffer queue is
locked. If the MENRQAUNLCK bit is set in MDREG3
this bit will be auto-cleared after the user programmed
delay or on receive buffer empty, otherwise, the node
processor has to clear the lock by issuing a command.
The auto-unlock will not work if host interface is not used
to read the receive queue and the lock can be cleared
only by the node processor. This feature can be
enabled/disabled in memory active or initialization
mode only. Once enabled/disabled the feature applies
to both the receive queues (if selected using MENDRCV
in MDREG3).
AMD
31