ZL50050GAC ZARLINK [Zarlink Semiconductor Inc], ZL50050GAC Datasheet - Page 59

• Manufacturer Part Number: ZL50050GAC
• Description: 8 K-Channel Digital Switch with High Jitter Tolerance, Per Stream Rate Conversion (2, 4, 8, 16, or 32 Mbps), and 32 Inputs and 32 Outputs
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

14.4
Addresses 0003h to 0012
Sixteen Local Input Channel Delay Registers (LCDR0 to LCDR15) allow users to program the input channel delay
for the Local input data streams LSTi0-15. The maximum possible adjustment is 511 channels and the LCDR0 to
LCDR15 registers are configured as follows:
Non-32 Mbps Mode, n = 0 to 7
Bit
2
1
0
(where n = 0 to 15 for Local
for Local 32 Mbps Mode)
Local Input Channel Delay Registers (LCDR0 to LCDR15)
SBERRXL
SBERTXL
LCDRn Bit
PRBSL
Name
15:9
8:0
Table 21 - Bit Error Rate Test Control Register (BERCR) Bits (continued)
Reset
Value
Table 22 - Local Input Channel Delay Register (LCDRn) Bits
0
0
0
H
.
Start Bit Error Rate Receiver for Local
A LOW to HIGH transition enables the Local BER receiver. The receiver monitors
incoming data for reception of the seed value. When detected, the LOCK state is
indicated (LOCKL), the receiver compares the incoming bits with the reference
generator for bit equality, and increments the Local Bit Error Register (LBCR) on
each failure.
When LOW, bit comparison is disabled and the error count is frozen.
Start Bit Error Rate Transmitter for Local
A LOW to HIGH transition enables the Local BER transmission.
When LOW, Local transmission is disabled.
BER Mode Select for Local
When HIGH, a PRBS sequence of length 2
When LOW, a PRBS sequence of length 2
Reserved
LCD[8:0]
Name
Zarlink Semiconductor Inc.
Reset
Value
ZL50050
0
0
59
Reserved
Must be set to 0 for normal operation
Local Channel Delay Register
The binary value of these bits refers to the channel
delay value for the Local input stream.
Description
15
23
-1 is selected for the Local port.
-1 is selected for the Local port.
Description
Data Sheet
: