ZL50115 ZARLINK [Zarlink Semiconductor Inc], ZL50115 Datasheet - Page 65
ZL50115
Manufacturer Part Number
ZL50115
Description
32, 64 and 128 Channel CESoP Processors
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
1.ZL50115.pdf
(95 pages)
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ZL50115GAG2
Manufacturer:
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10.0
All memory map and register definitions are included in the ZL50115/16/17/18/19/20 Programmers Model
document.
11.0
Absolute Maximum Ratings*
* Exceeding these figures may cause permanent damage. Functional operation under these conditions is not guaranteed. Voltage
measurements are with respect to ground (V
* The core and PLL supply voltages must never be allowed to exceed the I/O supply voltage by more than 0.5 V during power-up. Failure to
observe this rule could lead to a high-current latch-up state, possibly leading to chip failure, if sufficient cross-supply current is available. To be
safe ensure the I/O supply voltage supply always rises earlier than the core and PLL supply voltages.
I/O Supply Voltage
Core Supply Voltage
PLL Supply Voltage
Input Voltage
Input Voltage (5 V tolerant inputs)
Continuous current at digital inputs
Continuous current at digital outputs
Package power dissipation
Storage Temperature
DC Characteristics
Memory Map and Register Definitions
Parameter
Figure 24 - Jitter Transfer Function - Detail
SS
) unless otherwise stated.
ZL50115/16/17/18/19/20
Zarlink Semiconductor Inc.
V
V
Symbol
DD_CORE
V
DD_PLL
V
DD_IO
65
PD
TS
I
V
I_5V
I
IN
O
I
Min.
-0.5
-0.5
-0.5
-0.5
-0.5
-55
-
-
-
V
DD
Max.
+125
2.38
±10
±15
5.0
2.5
2.5
7.0
+ 0.5
Data Sheet
Units
mA
mA
°C
W
V
V
V
V
V
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