AM79Q031 ETC1 [List of Unclassifed Manufacturers], AM79Q031 Datasheet - Page 30

• Manufacturer Part Number: AM79Q031
• Description: Quad Subscriber Line Audio-Processing Circuit (QSLAC) Devices
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

30
(8 kHz)
FS
CD1
Notes:
Programmed value of GK0–GK3 determines clock rate (1–15 ms) of six-state counter.
If GK value = 0, counter is bypassed and no buffering occurs.
Six-state up/down counter: Counts up when input is high; counts down when input is low.
DSH0–DSH3 programmed value is common for all 4 channels, but debounce counter is separate per channel
Debounce Counter: Output goes high after counting to programmed (DSH) number of 1 ms clocks;
Notes:
* Transparent latch: Output follows input when EN is high; output holds last state when EN is low
Sampling Interval
D
Figure 11. MPI Real-Time Data Register or GCI Upstream SC Channel Data
CD2 or CD1B
Ground-Key
Q
(1–15 ms)
GK0–GK3
1 kHz
D
Counter is reset for CD1 input changes at 125 µs sample period.
Output goes and stays high when maximum count is reached;
output goes and stays low when counts down to zero.
Q
Clock Divider
(1–15 ms
clock output)
a. Loop Detect Debounce Filter
RST
Am79Q02/021/031 Data Sheet
b. Ground-Key Filter
D
Q
Six-State
Up/Down
Counter
UP/DN
Debounce Period
8
Q
DSH0–DSH3
(0–15 ms)
Debounce Counter
CK
MUX
GK=0
GK=0
GK
RST
Q
EN/HOLD
D
CDB
*
Q
CDA