ZL50405GDC ZARLINK [Zarlink Semiconductor Inc], ZL50405GDC Datasheet - Page 110
ZL50405GDC
Manufacturer Part Number
ZL50405GDC
Description
Managed5-Port 10/100 M Ethernet Switch
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
1.ZL50405GDC.pdf
(132 pages)
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12.3.10.9
CPU Address EAA – EAB
Accessed by CPU (RO)
Bit [11]:
Bit [12]:
Bit [13]:
Bits [15:14]:
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
Bit [4]:
Bit [5]:
Bit [6]:
Bit [7]:
Bit [8]:
Bit [9]:
Bit [10]:
Bit [11]:
Bit [12]:
Bit [13]:
Bits [15:14]:
PRTQOSST9A, PRTQOSST9B (MMAC port)
priority 1 MC queue full
priority 2 MC queue full
Priority 3 MC queue full
Reserved
Source port reservation low
No source port buffer left
Unicast congestion detected on best effort queue
Reserved
Priority queue 1 reach L1 WRED level
Priority queue 1 reach L2 WRED level
Priority queue 2 reach L1 WRED level
Priority queue 2 reach L2 WRED level
Priority queue 3 reach L1 WRED level
Priority queue 3 reach L2 WRED level
Priority 0 MC queue full
Priority 1 MC queue full
Priority 2 MC queue full
Priority 3 MC queue full
Reserved
15
PQSTB
Zarlink Semiconductor Inc.
ZL50405
110
PQSTA
0
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