ZL50408GDC ZARLINK [Zarlink Semiconductor Inc], ZL50408GDC Datasheet - Page 106

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ZL50408GDC

Manufacturer Part Number
ZL50408GDC
Description
Managed 8-Port 10/100M 1-Port 10/100/1000M Ethernet Switch
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
13.3.10.3
CPU Address E02, E03
Accessed by CPU (RO)
13.3.10.4
CPU Address E10-E14
Accessed by CPU (R/W)
Disable timeout reset on selected state machine status.
See Programming Timeout Reset application note, ZLAN-41, for more information.
13.3.10.5
CPU Address E80-E83
Accessed by CPU (RO)
13.3.10.6
CPU Address E90+n
Accessed by CPU (RO)
TESTOUT0, TESTOUT1 – Testmux Output [7:0], [15:8]
MASK0-MASK4 – Timeout Reset Mask
BOOTSTRAP0 – BOOTSTRAP3
PRTFSMST0~9
Bit [15:0]:
Bit [23:16]:
Bit [25:24]:
Bit [31:26]:
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
31
BT3
TX FSM NOT idle for 5 sec
TX FIFO control NOT idle for 5 sec
RX SFD detection NOT idle for 5 sec
RXINF NOT idle for 5 sec
23
Bootstrap value from TSTOUT[15:0]:
Bootstrap value from M[7:0]_TXEN
Bootstrap value from M9_TXEN, M9_TXER
Reserved
BT2
Bit [6:0]: TSTOUT[6:0]
Bit [8:7]: Invert of TSTOUT[8:7]
Bit [9]: TSTOUT[11]
Bit [10]: TSTOUT[9]
Bit [11]: TSTOUT[10]
Bit [14:12]: TSTOUT[14:12]
Bit [15]: Always 0
Bit [16]: M0_TXEN
Bit [17]: M1_TXEN
...
Bit [23]: M7_TXEN
Zarlink Semiconductor Inc.
15
ZL50408
BT1
106
BT0
0
Data Sheet

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