M36P0R9070E0ZAC STMICROELECTRONICS [STMicroelectronics], M36P0R9070E0ZAC Datasheet
M36P0R9070E0ZAC
Available stocks
Related parts for M36P0R9070E0ZAC
M36P0R9070E0ZAC Summary of contents
Page 1
Mbit (x16, Multiple Bank, Multi-Level, Burst) Flash Memory 128 Mbit (Burst) PSRAM, 1.8V Supply, Multi-Chip Package Features summary Multi-chip package – 1die of 512 Mbit (32Mb x 16, Multiple Bank, Multi-Level, Burst) Flash Memory – 1 die of 128Mbit ...
Page 2
Contents 1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 3
M36P0R9070E0 6 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 4
List of tables Table 1. Logic Diagram ...
Page 5
M36P0R9070E0 List of figures Figure 1. TFBGA Connections (Top view through package ...
Page 6
... Multiple Bank Flash memory (the M58PR512J). 128 Mbit PSRAM (the M69KB128AA). This datasheet should be read in conjunction with the M58PR512J and M69KB128AA datasheets, which are available from www.st.com. Recommended operating conditions do not allow more than one memory to be active at the same time. ...
Page 7
M36P0R9070E0 Table 2. Signal Names (1) A0-A24 DQ0-DQ15 V DDQ V PPF V DDF V CCP WAIT NC DU Flash Memory DPD F PSRAM E P ...
Page 8
Summary description Figure 1. TFBGA Connections (Top view through package DDQ ...
Page 9
... Clock (K) The Clock input pin is common to the Flash memory and PSRAM components. For details of how the Clock signal behaves, please refer to the datasheets of the respective memory components: M69KB128AA for the PSRAM and M58PR512J for the Flash memory. and Table 2., Signal ...
Page 10
Signal descriptions 2.5 Wait (WAIT) WAIT is an output pin common to the Flash memory and PSRAM components. However the WAIT signal does not behave in the same way for the PSRAM and the Flash memory. For details of ...
Page 11
M36P0R9070E0 The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied to V (refer to Table 8., Flash Memory DC Characteristics - RPH 2.11 PSRAM Chip Enable input (E The Chip Enable input ...
Page 12
Signal descriptions 2.17 Deep Power-Down input (DPD The Deep Power-Down input is used to place the device in a Deep Power-Down mode.When the device is in Deep Power-Down mode, the memory cannot be modified and data is protected. For ...
Page 13
M36P0R9070E0 2.22 V Ground the common ground reference for all voltage measurements in the Flash (core and I/O SS Buffers) and PSRAM chips. It must be connected to the system ground. Note: Each Flash memory device in ...
Page 14
Functional description 3 Functional description The PSRAM and Flash memory components have separate power supplies but share the same grounds. They are distinguished by two Chip Enable inputs: E PSRAM. Recommended operating conditions do not allow more than one ...
Page 15
M36P0R9070E0 Table 3. Main Operating Modes G Operation Flash Read Flash Write IL IH Flash Address Latch Flash Output Disable V Flash Standby X ...
Page 16
Maximum rating 4 Maximum rating Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any ...
Page 17
M36P0R9070E0 5 DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the ...
Page 18
DC and AC parameters Figure 4. AC Measurement Load Circuit Table 6. Capacitance Symbol Parameter C Input Capacitance IN C Output Capacitance OUT 1. Sampled only, not 100% tested. 18/26 V CCQ DEVICE UNDER TEST ...
Page 19
M36P0R9070E0 Table 7. Flash Memory DC Characteristics - Currents Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO Supply Current Asynchronous Read (f=5MHz) Supply Current Page Read (f=13MHz) Supply Current I DD1 Synchronous Read (f=66MHz) Supply Current ...
Page 20
DC and AC parameters Table 8. Flash Memory DC Characteristics - Voltages Symbol Parameter V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage Program Voltage-Logic PP1 ...
Page 21
M36P0R9070E0 Table 9. PSRAM DC Characteristics Refreshed Symbol Parameter Array (3) V Output High Voltage OH (3) Output Low Voltage V OL (1) Input High Voltage V IH (2) Input Low Voltage Input Leakage Current LI I ...
Page 22
Package mechanical 6 Package mechanical In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second-level interconnect. The category of Second-Level Interconnect is marked on the package and on the inner ...
Page 23
M36P0R9070E0 Table 10. Stacked TFBGA107 8x11mm - 9x12 active ball array, 0.8mm pitch, package data Symbol Typ 0.85 b 0.35 D 8.00 D1 6.40 ddd E 11.00 E1 8.80 e 0.80 FD 0.80 FE 1.10 SE 0.40 ...
Page 24
Part numbering 7 Part numbering Table 11. Ordering Information Scheme Example: Device Type M36 = Multi-Chip Package (Multiple Flash + PSRAM) Flash 1 Architecture P = Multi-Level, Multiple Bank, Large Buffer Flash 2 Architecture Die Operating ...
Page 25
M36P0R9070E0 8 Revision history Table 12. Document revision history Date Revision 28-Nov-2005 1 Changes Initial release. 8 Revision history 25/26 ...
Page 26
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. ...