M36P0R9070E0_06 STMICROELECTRONICS [STMicroelectronics], M36P0R9070E0_06 Datasheet
M36P0R9070E0_06
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M36P0R9070E0_06 Summary of contents
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Mbit (x16, Multiple Bank, Multi-Level, Burst) Flash memory 128 Mbit (Burst) PSRAM, 1.8V supply, Multi-Chip Package Feature summary Multi-Chip Package – 1 die of 512 Mbit (32Mb x 16, Multiple Bank, Multi-Level, Burst) Flash Memory – 1 die of ...
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Contents Contents 1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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M36P0R9070E0 6 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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M36P0R9070E0 List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... It should be read in conjunction with the M58PRxxxJ and M69KB128AB datasheets, where all specifications required to operate the Flash memory and PSRAM components are fully detailed. The M58PR512J and M69KB128AB datasheets are available from www.st.com. Recommended operating conditions do not allow more than one memory to be active at the same time ...
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M36P0R9070E0 Table 1. Signal names (1) A0-A24 DQ0-DQ15 V DDQ V PPF V DDF V CCP WAIT NC DU Flash Memory DPD F PSRAM E P ...
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Summary description Figure 2. TFBGA connections (top view through package DDQ 8/23 2 ...
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... Flash memory. 2.4 Clock (K) The Clock input pin is common to the Flash memory and PSRAM components. For details of how the Clock signal behaves, please refer to the datasheets of the respective memory components: M69KB128AB for the PSRAM and M58PR512J for the Flash memory. and Table 1., Signal ...
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Signal descriptions 2.5 Wait (WAIT) WAIT is an output pin common to the Flash memory and PSRAM components. However the WAIT signal does not behave in the same way for the PSRAM and the Flash memory. For details of how ...
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M36P0R9070E0 2.10 Flash Reset (RP The Reset input provides a hardware reset of the Flash memories. When Reset memory is in Reset mode: the outputs are high impedance and the current consumption is reduced to the Reset ...
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Signal descriptions 2.17 Deep Power-Down input (DPD The Deep Power-Down input is used to place the device in a Deep Power-Down mode.When the device is in Deep Power-Down mode, the memory cannot be modified and data is protected. For further ...
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M36P0R9070E0 2.22 V Ground the common ground reference for all voltage measurements in the Flash (core and SS I/O Buffers) and PSRAM chips. It must be connected to the system ground. Note: Each Flash memory device in ...
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Functional description 3 Functional description The PSRAM and Flash memory components have separate power supplies but share the same grounds. They are distinguished by two Chip Enable inputs: E the PSRAM. Recommended operating conditions do not allow more than one ...
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M36P0R9070E0 Table 2. Main operating modes Operation Bus Read Bus Write Address Latch Output Disable V V ...
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Maximum rating 4 Maximum rating Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other ...
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M36P0R9070E0 5 DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the ...
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... DC and AC parameters Figure 5. AC measurement load circuit Table 5. Capacitance Symbol OUT 1. Sampled only, not 100% tested. Please refer to the M58PRxxxJ and M69KB128AB datasheets for further DC and AC characteristic values and illustrations. 18/23 DEVICE UNDER TEST Z 0 (1) Parameter Test Condition Input Capacitance V IN ...
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M36P0R9070E0 6 Package mechanical In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second-level interconnect. The category of Second-Level Interconnect is marked on the package and on the inner box label, ...
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Package mechanical Table 6. Stacked TFBGA107 8 × 11mm - 9 × 12 active ball array, 0.8mm pitch, package mechanical data Symbol ddd 20/23 millimeters Typ Min Max ...
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M36P0R9070E0 7 Part numbering Table 7. Ordering information scheme Example: Device Type M36 = Multi-Chip Package (Multiple Flash + PSRAM) Flash 1 Architecture P = Multi-Level, Multiple Bank, Large Buffer Flash 2 Architecture Die Operating Voltage R ...
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... Initial release. Document status promoted from Preliminary data to full Datasheet. Document updated to latest version of M58PRxxxJ datasheet, DC characteristics tables removed (for values refer to M58PRxxxJ and M69KB128AB datasheets). PSRAM part replaced by M69KB128AB ball Figure 2: TFBGA connections (top view through package). T min and V ...
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M36P0R9070E0 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at ...