9DB102BFILF IDT [Integrated Device Technology], 9DB102BFILF Datasheet
9DB102BFILF
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9DB102BFILF Summary of contents
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Two Output Differential Buffer for PCIe Gen1 & Gen2 Description The ICS9DB102 zero-delay buffer supports PCI Express clocking requirements. The ICS9DB102 is driven by a differential SRC output pair from an ICS CK410/CK505-compliant main clock. It attenuates jitter on the ...
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ICS9DB102 Two Output Differential Buffer for PCIe Gen1 & Gen2 Pin Configuration PLL_BW 1 CLK_INT 2 CLK_INC 3 **CLKREQ0# 4 VDD 5 GND 6 PCIEXT0 7 PCIEXC0 8 VDD 9 SMBDAT 10 Note: Pins preceeded by '**' have internal 120K ...
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ICS9DB102 Two Output Differential Buffer for PCIe Gen1 & Gen2 Absolute Max Symbol Parameter VDDA 3.3V Core Supply Voltage VDD 3.3V Output Supply Voltage Ts Storage Temperature Tcase Case Temperature Input ESD protection human body model ESD prot Electrical Characteristics ...
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ICS9DB102 Two Output Differential Buffer for PCIe Gen1 & Gen2 Electrical Characteristics - PCIEX 0.7V Current Mode Differential Pair T = Tambient 3.3 V +/-5 PARAMETER SYMBOL Current Source Output Zo Impedance Voltage High VHigh ...
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ICS9DB102 Two Output Differential Buffer for PCIe Gen1 & Gen2 Electrical Characteristics - PLL Parameters T = Tambient; Supply Voltage Group Parameter PLL Jitter Peaking j peak-hibw PLL Jitter Peaking j peak-lobw PLL Bandwidth pll HIBW PLL ...
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ICS9DB102 Two Output Differential Buffer for PCIe Gen1 & Gen2 Common Recommendations for Differential Routing L1 length, route as non-coupled 50ohm trace L2 length, route as non-coupled 50ohm trace L3 length, route as non-coupled 50ohm trace Rs Rt Down Device ...
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ICS9DB102 Two Output Differential Buffer for PCIe Gen1 & Gen2 Alternative Termination for LVDS and other Common Differential Signals (figure 3) Vdiff Vp-p Vcm 0.45v 0.22v 1.08 0.58 0.28 0.6 0.80 0.40 0.6 0.60 0.3 1.2 R1a = R1b = ...
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ICS9DB102 Two Output Differential Buffer for PCIe Gen1 & Gen2 General SMBus serial interface information for the ICS9DB102 How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D4 • ICS clock will ...
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ICS9DB102 Two Output Differential Buffer for PCIe Gen1 & Gen2 SMBus Table: Device Control Register, READ/WRITE ADDRESS (D4/D5) Byte 0 Pin # Name Bit 7 - SW_EN - Bit 6 Bit Bit 4 Bit ...
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ICS9DB102 Two Output Differential Buffer for PCIe Gen1 & Gen2 SMBus Table: DEVICE ID Byte 4 Pin # Name - Bit 7 - Bit 6 Bit 5 - Bit 4 - Bit Bit 2 Bit 1 - ...
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ICS9DB102 Two Output Differential Buffer for PCIe Gen1 & Gen2 20-Pin SSOP Package Drawing and Dimensions ® IDT Two Output Differential Buffer for PCIe Gen1 & Gen2 20-Lead, 150 mil SSOP (QSOP) In Millimeters SYMBOL COMMON DIMENSIONS MIN MAX A ...
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... Ordering Information Part / Order Number Shipping Packaging 9DB102BFLF Tubes 9DB102BFLFT Tape and Reel 9DB102BFILF Tubes 9DB102BFILFT Tape and Reel 9DB102BGLF Tubes 9DB102BGLFT Tape and Reel 9DB102BGILF Tubes 9DB102BGILFT Tape and Reel "LF" after the package code are the Pb-Free configuration and are RoHS compliant. ...
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ICS9DB102 Two Output Differential Buffer for PCIe Gen1 & Gen2 Revision History Rev. Originator Issue Date Description 1. Added Phase Noise Parameters, Updated input to output delay values. 2. PLL BW moved to PLL parameters table. F 8/6/2007 3. Added ...