9DB106 IDT [Integrated Device Technology], 9DB106 Datasheet
9DB106
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9DB106 Summary of contents
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... Six Output Differential Buffer for PCIe Gen 2 Description The 9DB106 zero-delay buffer supports PCIe Gen1 and Gen2 clocking requirements. The 9DB106 is driven by a differential SRC output pair from an IDT CK410/CK505-compliant main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking ...
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... PCIEXC2 12 VDD 13 SMBDAT 14 Note:Pins preceeded have internal 120K ohm pull down resistors 28-pin SSOP & TSSOP Description PCI Express Outputs SMBUS IREF 2 28 VDDA 27 GNDA 26 IREF 25 vCLKR EQ4# 24 PCIEXT5 23 PCIEXC5 22 VDD 21 GND 20 PCIEXT4 19 PCIEXC4 18 PCIEXT3 17 PCIEXC3 16 VDD 15 SMBCLK 9DB106 REV K 04/20/11 ...
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... This pin establishes the reference for the differential current-mode output pairs. It requires a fixed precision resistor to ground. OUT 475ohm is the standard value for 100ohm differential impedance. Other impedances require different values. See data sheet. PWR Ground pin for the PLL core. PWR 3.3V power for the PLL core. 3 DESCRIPTION 9DB106 REV K 04/20/11 ...
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... MIN TYP MAX 0.3 0 -200 130 150 100 105 7 5 4.5 1 2.7 5.5 0.4 4 1000 300 9DB106 UNITS NOTES V 1 ° ° UNITS Notes ° ° 1,2 V 1,2 uA 1,2 uA 1 ...
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... TYP MAX 600 800 1150 V - 300 0 300 SS 300 1000 300 1450 0 125 Min Typ Max Units 2.5 3 MHz 0.4 0.5 1 MHz 40 108 2.7 3.1 ps rms 2.2 3.1 ps rms 1 rms 9DB106 UNITS NOTES V/ns 1 Notes dB 1,4 dB 1,4 1,5 1,5 ps 1,2,3 1,2,3 1,2,3 1,2,3 REV K 04/20/11 ...
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... Rise Time Variation Fall Time Variation Input to Output Delay t Duty Cycle Output-to-Output Skew Jitter, Cycle to cycle t jcyc-cyc 1 Guaranteed by design and characterization, not 100% tested in production. 2 The 9DB106 does not add a ppm error to the input clock /(3xR ). For R = 475 REF IDT ® ...
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... Dimension or Value Unit 0.5 max inch 0.2 max inch 0.2 max inch 33 ohm 49.9 ohm inch 1.8 min to 14.4 max inch inch 0.225 min to 12.6 max inch L4 L4' Rt PCI Express Down Device REF_CLK Input L4 L4' Rt PCI Express Add-in Board REF_CLK Input L3 9DB106 Figure REV K 04/20/11 ...
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... Component Value R5a, R5b 8.2K 5% R6a, R6b 0.1 µF Vcm 0.350 volts 3.3 Volts R5a L4 L4' R6a 8 R4 Note 100 100 100 ICS874003i-02 input compatible 100 Standard LVDS R4 L4 L4' R2b Down Device REF_CLK Input L3 Note R5b R6b PCIe Device REF_CLK Input 9DB106 REV K 04/20/11 ...
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... Six Output Differential Buffer for PCIe Gen 2 General SMBus serial interface information for the 9DB106 How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D4 • IDT clock will acknowledge • Controller (host) sends the begining byte location = N • ...
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... SMBus 1 by device pins registers - Low BW High BW 1 PLL enabled 1 (ZDB mode PWD - Disable Enable Disable Enable 1 Disable Enable Disable Enable PWD - PWD - - 9DB106 REV K 04/20/11 ...
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... Writing to this BC6 RW register will BC5 RW configure how BC4 RW many bytes will be BC3 RW read back, default BC2 bytes. BC1 RW BC0 9DB106 PWD PWD REV K 04/20/11 ...
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... Reference Doc.: JEDEC Publication 95, MO-150 10-0033 12 In Inches COMMON DIMENSIONS MIN MAX -- .079 .002 -- .065 .073 .009 .015 .0035 .010 SEE VARIATIONS .291 .323 .197 .220 0.0256 BASIC .022 .037 SEE VARIATIONS 0° 8° D (inch) MIN MAX .390 .413 9DB106 REV K 04/20/11 ...
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... Tape and Reel 9DB106BGLF Tubes 9DB106BGLFT Tape and Reel 9DB106BFILF Tubes 9DB106BFILFT Tape and Reel 9DB106BGILF Tubes 9DB106BGILFT Tape and Reel "LF" after the package code are the Pb-Free configuration and are RoHS compliant. "B" is the device revision designator (will not correlate to the datasheet revision). ...
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... Six Output Differential Buffer for PCIe Gen 2 Revision History Rev. Originator Issue Date Description 1. Changed Output to Output skew from 30ps to 45ps. 2. Changed PLL mode jitter from 40ps to 35ps. 3. Changed Bypass mode additive jitter from 25ps to 35ps. B RDW 9/12/2005 4. Updated LF Ordering Information. ...