9DB1933AKLF IDT [Integrated Device Technology], 9DB1933AKLF Datasheet
9DB1933AKLF
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9DB1933AKLF Summary of contents
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Nineteen Output Differential Buffer for PCIe Gen3 Recommended Application 19 output PCIe Gen3 zero-delay/fanout buffer General Description The 9DB1933 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB1933 is driven by a ...
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... CKPWRGD/ DIF_IN/ PD# DIF_IN# 1 Running 0 X Power Groups Pin Number VDD GND 3 2 5,11,27,47,63 10,28,46,64 ® IDT Nineteen Output Differential Buffer for PCIe Gen3 9DB1933AKLF OUTPUTS PLL State DIF/DIF# Running ON Hi-Z OFF Description PLL, Analog DIF clocks 2 54 OE14# 53 DIF_13# 52 DIF_13 51 OE13# 50 DIF_12# 49 DIF_12 48 OE12# ...
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Nineteen Output Differential Buffer for PCIe Gen3 Pin Description PIN # PIN NAME PIN TYPE 1 IREF 2 GNDA PWR 3 VDDA PWR 4 HIGH_BW# 5 VDD PWR 6 DIF_0 7 DIF_0# 8 DIF_1 9 DIF_1# 10 GND PWR ...
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Nineteen Output Differential Buffer for PCIe Gen3 Pin Description (cont.) PIN # PIN NAME PIN TYPE 37 OE9# 38 DIF_9 39 DIF_9# 40 OE10# 41 DIF_10 42 DIF_10# 43 OE11# 44 DIF_11 45 DIF_11# 46 GND 47 VDD 48 ...
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Nineteen Output Differential Buffer for PCIe Gen3 Electrical Characteristics - Absolute Maximum Ratings PARAMETER SYMBOL 3.3V Core Supply Voltage VDDA 3.3V Logic Supply Voltage VDD Input Low Voltage V IL Input High Voltage V IH Input High Voltage V ...
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Nineteen Output Differential Buffer for PCIe Gen3 Electrical Characteristics - Clock Input Parameters Supply Voltage VDD = 3.3 V +/-5% COM IND; PARAMETER SYMBOL Input High Voltage - DIF_IN V IHDIF Input Low Voltage ...
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Nineteen Output Differential Buffer for PCIe Gen3 Electrical Characteristics - Output Duty Cycle, Jitter, Skew and PLL Characterisitics Supply Voltage VDD = 3.3 V +/-5% COM; PARAMETER SYMBOL PLL Bandwidth BW t PLL Jitter Peaking JPEAK ...
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Nineteen Output Differential Buffer for PCIe Gen3 Electrical Characteristics - PCIe Phase Jitter Parameters Supply Voltage VDD = 3.3 V +/-5% COM; PARAMETER SYMBOL t jphPCIeG1 t jphPCIeG2 Phase Jitter, PLL Mode t jphPCIeG3 t jphPCIeG1 ...
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Nineteen Output Differential Buffer for PCIe Gen3 Clock Periods Differential Outputs with Spread Spectrum Enabled Measurement Window 1 Clock 1us Symbol Lg- -SSC Absolute Short-term Period Average Definition Minimum Minimum Absolute Absolute Period Period 9.87400 9.99900 DIF DIF 100 ...
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Nineteen Output Differential Buffer for PCIe Gen3 Common Recommendations for Differential Routing L1 length, route as non-coupled 50ohm trace L2 length, route as non-coupled 50ohm trace L3 length, route as non-coupled 50ohm trace Rs Rt Down Device Differential Routing ...
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Nineteen Output Differential Buffer for PCIe Gen3 Alternative Termination for LVDS and other Common Differential Signals (figure 3) Vdiff Vp-p Vcm 0.45v 0.22v 1.08 0.58 0.28 0.6 0.80 0.40 0.6 0.60 0.3 1.2 R1a = R1b = R1 R2a ...
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Nineteen Output Differential Buffer for PCIe Gen3 General SMBus serial interface information for the 9DB1933 How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address DC • ICS clock will acknowledge • ...
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Nineteen Output Differential Buffer for PCIe Gen3 SMBusTable: Reserved Register Byte 0 Pin # Name - Bit 7 Bit 6 - Bit 5 - Bit 4 - Bit 3 - Bit 2 - Bit Bit 0 ...
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Nineteen Output Differential Buffer for PCIe Gen3 SMBusTable: Output Enable Readback Register Byte 4 Pin # Name 69 Readback - OE17_18# Input Bit 7 60 Readback - OE15_16# Input Bit 6 Bit 5 54 Bit 4 Bit 3 51 ...
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Nineteen Output Differential Buffer for PCIe Gen3 SMBusTable: Output Control Register Byte 8 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 DIF_18 Bit 3 DIF_17 Bit 2 DIF_16 DIF_15 Bit 1 DIF_14 Bit 0 SMBusTable: Reserved ...
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... N E Ordering Information Part / Order Number Shipping Packaging 9DB1933AKLF 9DB1933AKLFT Tape and Reel “LF” after the package code denotes the Pb-Free configuration, RoHS compliant. “A” is the device revision designator (will not correlate with the datasheet revision). IDT ® Nineteen Output Differential Buffer for PCIe Gen3 ...
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Nineteen Output Differential Buffer for PCIe Gen3 Revision History Rev. Issue Date Who Description 0.1 7/7/2010 RDW Initial release 1. Updated 'PWD' to 'Default' in SMBus column headings A 7/12/2010 RDW 2. Updated electrical tables with char data 3. ...