9DB1933AKLF IDT [Integrated Device Technology], 9DB1933AKLF Datasheet - Page 4

• Manufacturer Part Number: 9DB1933AKLF
• Description: Nineteen Output Differential Buffer for PCIe Gen3
• Manufacturer: IDT [Integrated Device Technology]

Pin Description (cont.)
IDT
PIN #
9DB1933
Nineteen Output Differential Buffer for PCIe Gen3
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
®
Nineteen Output Differential Buffer for PCIe Gen3
OE9#
DIF_9
DIF_9#
OE10#
DIF_10
DIF_10#
OE11#
DIF_11
DIF_11#
GND
VDD
OE12#
DIF_12
DIF_12#
OE13#
DIF_13
DIF_13#
OE14#
DIF_14
DIF_14#
CKPWRGD/PD#
DIF_15
DIF_15#
OE_15_16#
DIF_ 16
DIF_16#
VDD
GND
DIF_17
DIF_17#
DIF_18
DIF_18#
OE_17_18#
DIF_IN
DIF_IN#
SMB_A2_PLLBYP#
PIN NAME
PIN TYPE
PWR
PWR
PWR
PWR
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
Active low input for enabling DIF pair 9.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pair 10.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pair 11.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Ground pin.
Power supply, nominal 3.3V
Active low input for enabling DIF pair 12.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pair 13.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pair 14.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
A rising edge samples latched inputs and release Power Down Mode, a low
puts the part into power down mode and tristates all outputs.
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pair 15 and 16.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Power supply, nominal 3.3V
Ground pin.
0.7V differential true clock output
0.7V differential Complementary clock output
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pair 17, 18.
1 = tri-state outputs, 0 = enable outputs
0.7 V Differential TRUE input
0.7 V Differential Complementary Input
SMBus address bit 2. When Low, the part operates as a fanout buffer with the
PLL bypassed. When High, the part operates as a zero-delay buffer (ZDB) with
the PLL operating.
0 = fanout mode (PLL bypassed), 1 = ZDB mode (PLL used)
4
DESCRIPTION
1676A—07/12/10