L-FW323-06-DB AGERE [Agere Systems], L-FW323-06-DB Datasheet - Page 36

• Manufacturer Part Number: L-FW323-06-DB
• Description: PCI PHY/Link Open Host Controller Interface
• Manufacturer: AGERE [Agere Systems]

FW323 06 1394a
PCI PHY/Link Open Host Controller Interface
Internal Registers
Power Management CSR PCI-to-PCI Bridge Support Extensions
This register returns 00h when read since the FW323 does not provide PCI-to-PCI bridging.
Offset:
Default:
Type:
Reference:
Power Management Data
The Power Management (PM) Data register set is comprised of 16 eight-bit registers, providing more detailed power
management information about the device. All 16 registers will return 00h by default. The first eight registers are
assigned to single function devices, and the second eight are reserved for use by multifunction devices (see Table
18). The FW323 supports programmability, via the serial EEPROM, of the first eight registers in the PM data com-
plex. Software uses the DATA_SELECT and DATA_SCALE fields within the Power Management Control and Status
register to select and scale the desired PM data entry. Note that if the serial EEPROM is used to program nonzero
values into PM DATA, then the AUX_PWR field should be programmed to a zero value via the serial EEPROM and
vice versa. This is to comply with the PCI Specification, which states that these two functions must be implemented
mutually exclusive of one another. The FW323 does not enforce this, and therefore, it is up to the creator of the serial
EEPROM image to ensure that these two fields are used mutually exclusive of one another.
Offset:
Default:
Type:
Reference:
Table 18. Power Management Data Register Description
(Derived from Table 10 of the PCI Power Management Interface Specification, Revision 1.1.)
CardBus Function Registers
The FW323 06, when used in a CardBus application, provides a set of four 32-bit registers: Function Event, Function
Event Mask, Function Present State, and Function Force Event. These registers are located in memory space start-
ing at the location given by the CISTPL_CONFIG_CB tuple in the CIS and the CardBus Base Address register.
These registers support status changed notification through the CSTSCHG (PCI_PMEN) signal and functional inter-
rupt notification using the CINTN (PCI_INTAN) signal. The Function Event registers are only visible when
CardBusN = 0. For more information, refer to the Application Note Using the FW322 06/FW323 06 in CardBus Appli-
cations.
36
Data_Select
Value in
8—15
0
1
2
3
4
5
6
7
4Ah
00h
Read only
PCI Bus Power Management Interface Specification, Rev. 1.1, Section 3.2.5 and 1394 Open Host
Controller Interface Specification, Rev. 1.1, Section A.3.8.5 and A.3.8.6
4Bh
00h
Read Only
PCI Bus Power Management Interface Specification, Rev. 1.1, Section 3.2.6 and 1394 Open Host
Controller Interface Specification, Rev. 1.1, Section A.3.8.5 and A.3.8.6
and will return 00h when read)
Reserved (unused by FW323
D0 Power Consumed
D1 Power Consumed
D2 Power Consumed
D3 Power Consumed
D0 Power Dissipated
D1 Power Dissipated
D2 Power Dissipated
D3 Power Dissipated
Data Reported
(continued)
(CardBusN = 0)
Interpretation
0 = Unknown
Data_Scale
3 = 0.001x
Reserved
2 = 0.01x
1 = 0.1x
Units/Accuracy
Watts
TBD
Data Sheet, Rev. 1
December 2005
Agere Systems Inc.