IDT72V90823BC IDT, Integrated Device Technology Inc, IDT72V90823BC Datasheet - Page 12

• Manufacturer Part Number: IDT72V90823BC
• Description: IC DGTL SW 2048X2048 100-BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr
• Type: Multiplexerr

Specifications of IDT72V90823BC

• Circuit: 1 x 16:16
• Independent Circuits: 1
• Voltage Supply Source: Single Supply
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Output High, Low: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 72V90823BC

TABLE 8 — INTERFACE MODE SELECTION (IMS) REGISTER BITS
TABLE 9 — SERIAL DATA RATE SELECTION (16 INPUT X 16 OUTPUT)
IDT72V90823 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048
15-10
Read/Write Address:
Reset Value:
9-5
1-0
Bit
15
0
4
3
2
DR1
0
0
1
1
Unused
BPD4-0
(Block Programming Data)
BPE
(Begin Block Programming
OSB
(Output Stand By)
SFE
(Start Frame Evaluation)
DR0-1
(Data Rate Select)
14
Enable)
0
DR0
13
0
0
1
0
1
Name
01
0000
12
0
H
,
H
.
11
0
Must be zero for normal operation.
These bits carry the value to be loaded into the connection memory block whenever the memory block
programming feature is activated. After the MBP bit in the control register is set to 1 and the BPE bit is
set to 1, the contents of the bits BPD4-0 are loaded into bit 15 and 11 of the connection memory. Bit 10 to
bit 0 of the connection memory are set to 0.
A zero to one transition of this bit enables the memory block programming function. The BPE and
BPD4-0 bits in the IMS register have to be defined in the same write operation. Once the BPE bit is set
HIGH, the device requires two frames to complete the block programming. After the programming function
has finished, the BPE bit returns to zero to indicate the operation is completed. When the BPE = 1, the BPE
or MBP can be set to 0 to ensure proper operation. When BPE = 1, the other bit in the IMS register
must not be changed for two frames to ensure proper operation.
When ODE = 0 and OSB = 0, the output drivers of TX0 to TX15 are in high impedance mode. When
output drivers function normally.
A zero to one transition in this bit starts the frame evaluation procedure. When the CFE bit in the FAR
cycle, set this bit to zero for at least one frame.
Input/Output data rate selection. See Table 9 for detailed programming.
ODE= 0 and OSB = 1, the output driver of TX0 to TX15 function normally. When ODE = 1, TX0 to TX15
register changes from zero to one, the evaluation procedure stops. To start another fame evaluation
Data Rate Selected
10
0
2.048 Mb/s
4.096 Mb/s
8.192 Mb/s
Reserved
BPD4 BPD3 BPD2 BPD1 BPD0
9
8
7
12
6
Description
5
BPE
4
Master Clock Required
OSB
3
COMMERCIAL TEMPERATURE RANGE
16.384 MHz
4.096 MHz
8.192 MHz
Reserved
SFE
2
DR1
1
DR0
0