IDT72V90823BC IDT, Integrated Device Technology Inc, IDT72V90823BC Datasheet - Page 5

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IDT72V90823BC

Manufacturer Part Number
IDT72V90823BC
Description
IC DGTL SW 2048X2048 100-BGA
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Type
Multiplexerr
Datasheet

Specifications of IDT72V90823BC

Circuit
1 x 16:16
Independent Circuits
1
Voltage Supply Source
Single Supply
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-LBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Current - Output High, Low
-
Lead Free Status / RoHS Status
Not Compliant, Contains lead / RoHS non-compliant
Other names
72V90823BC

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Quantity
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Part Number:
IDT72V90823BC
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
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Manufacturer:
IDT
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Part Number:
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NOTE:
1. These pins are 5V tolerant.
PIN DESCRIPTION (CONTINUED)
IDT72V90823 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048
IM
AD0-7
D8-15
DTA
CCO
ODE
SYMBOL
(1)
(1)
(1)
(1)
(1)
(1)
CPU Interface Mode
Address/Data Bus
0 to 7
Data Bus 8-15
Data Transfer
Acknowledgment
Control Output
Output Drive Enable
NAME
I/O These pins are the eight least significant data bits of the microprocessor port. In multiplexed mode, these pins
I/O These pins are the eight most significant data bits of the microprocessor port.
I/O
O
O
I
I
When IM is HIGH, the microprocessor port is in the multiplexed mode. When IM is LOW, the microprocessor
port is in non-multiplexed mode.
are also the input address bits of the microprocessor port.
This active LOW output signal indicates that a data bus transfer is complete. When the bus cycle ends, this pin
drives HIGH and then goes high-impedance, allowing for faster bus cycles with a weaker pull-up resistor. A
pull-up resistor is required to hold a HIGH level when the pin is in high-impedance.
This is a 4.096, 8.192 or 16.384 Mb/s output containing 512, 1,024 or 2.048 bits per frame respectively. The
level of each bit is determined by the CCO bit in the connection memory. See External Drive Control Section.
This is the output enable control for the TX0 to TX15 serial outputs. When ODE input is LOW and the OSB
bit of the IMS register is LOW, TX0-15 are in a high-impedance state. If this input is HIGH, the TX0-15
output drivers are enabled. However, each channel may still be put into a high-impedance state by using the
per channel control bit in the connection memory.
5
DESCRIPTION
COMMERCIAL TEMPERATURE RANGE

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