MC74ACT257DR2G ON Semiconductor, MC74ACT257DR2G Datasheet - Page 2

• Manufacturer Part Number: MC74ACT257DR2G
• Description: IC MUX QUAD 2INPUT 3ST 16-SOIC
• Manufacturer: ON Semiconductor
• Series: 74ACTr
• Type: Multiplexerr

Specifications of MC74ACT257DR2G

• Circuit: 4 x 2:1
• Independent Circuits: 1
• Current - Output High, Low: 24mA, 24mA
• Voltage Supply Source: Single Supply
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Logical Function: Mux
• Configuration: 4 x 2:1
• Number Of Inputs: 8
• Number Of Outputs: 4
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 16
• Package Type: SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

multiplexer with 3−state outputs. It selects four bits of data
from two sources under control of a Common Data Select
input. When the Select input is LOW, the I
selected and when Select is HIGH, the I
selected. The data on the selected inputs appears at the
outputs in true (noninverted) form. The device is the logic
PIN NAME
TRUTH TABLE
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
PIN
S
OE
I
I
Z
0a
1a
The MC74AC257/74ACT257 is a quad 2−input
a
−Z
−I
−I
Output
Enable
0d
1d
d
OE
H
L
L
L
L
FUNCTIONAL DESCRIPTION
S
FUNCTION
Common Data Select Input
3−State Output Enable Input
Data Inputs from Source 0
Data Inputs from Source 1
3−State Multiplexer Outputs
OE I
Figure 2. Logic Symbol
Select
Input
Z
0a
a
S
X
H
H
L
L
I
1a
I
Z
0b
b
I
1b
I
X
X
X
H
L
I
Z
0
0c
c
Inputs
Data
I
1c
I
Z
I
H
0d
X
L
X
X
1
d
I
1d
1x
0x
inputs are
Outputs
inputs are
H
H
Z
Z
L
L
http://onsemi.com
2
implementation of a 4−pole, 2−position switch where the
position of the switch is determined by the logic levels
supplied to the Select input. The logic equations for the
outputs are shown below:
are forced to a high impedance state. If the outputs are tied
together, all but one device must be in the high impedance
state to avoid high currents that would exceed the maximum
ratings. Designers should ensure the Output Enable signals
to 3−state devices whose outputs are tied together are
designed so there is no overlap.
Z
Z
Z
Z
When the Output Enable input (OE) is HIGH, the outputs
a
b
c
d
= OE
= OE
= OE
= OE
•
•
•
•
(I
(I
(I
(I
1a
1b
1c
1d
•
•
•
•
S+I
S+I
S+I
S+I
0a
0c
0b
0d
•
•
•
•
S)
S)
S)
S)