HI-3584 HOLTIC [Holt Integrated Circuits], HI-3584 Datasheet
HI-3584
Related parts for HI-3584
HI-3584 Summary of contents
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... September 2006 GENERAL DESCRIPTION The HI-3584 from Holt Integrated Circuits is a silicon gate CMOS device for interfacing a 16-bit parallel data bus to the ARINC 429 serial bus. The HI-3584 design offers many enhancements to the industry standard HI-8282 architecture. The device provides two receivers each with label recognition FIFO, and an analog line receiver ...
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... Read Status Register if SEL=0, read Control Register if SEL=1 CLK INPUT Master Clock input TX CLK OUTPUT Transmitter Clock equal to Master Clock (CLK), divided by either 10 or 80. MR INPUT Master Reset, active low HI-3584 DESCRIPTION 5 HOLT INTEGRATED CIRCUITS 2 must be connect to the same supply) EN1 is high PL1. ...
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... FUNCTIONAL DESCRIPTION CONTROL WORD REGISTER The HI-3584 contains a 16-bit control register which is used to con- figure the device. The control register bits CR0 - CR15 are loaded from BD00 - BD15 when CWSTR is pulsed low. The control regis- ter contents are output on the databus when SEL = 1 and pulsed low ...
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... RIN2B GND FIGURE 1. ARINC RECEIVER INPUT HI-3584 The HI-3584 guarantees recognition of these levels with a common mode Voltage with respect to GND less than ±4V for the worst case condition (3.0V supply and 13V signal level). The tolerances in the design guarantee detection of the above levels, so the actual acceptance ranges are slightly larger ...
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... HF FF D/R FIFO LOAD CONTROL / LABEL / CONTROL DECODE BIT COMPARE LABEL MEMORY EOS ONES SHIFT REGISTER NULL SHIFT REGISTER ZEROS SHIFT REGISTER HI-3584 CR2(3) ARINC word CR6(9) ARINC word matches label Yes Yes Yes TO PINS R/W CONTROL ...
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... PL2 for receiver 2. word reception is suspended during the label memory write sequence. 32 BIT PARALLEL LOAD SHIFT REGISTER FIFO DATA BUS HI-3584 READING LABELS D/R1 or D/R2 (or both) both After the write that changes CR1 from the next 16 data reads of the selected receiver ( ...
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... Holt line drivers and line receivers. HIGH SPEED OPERATION The HI-3584 may be operated at clock frequencies beyond that re- quired for ARINC compliant operation. For operation at Master Clock (CLK) frequencies up to 5MHz, please contact Holt applica- tions engineering. ...
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... ARINC DATA BIT 31 BIT 32 D D/R DON'T CARE SEL EN DATA BUS t DATA BUS PL1 PL2 TX/R, HFT FFT , DATA BUS CWSTR HI-3584 DATA RATE - EXAMPLE PATTERN DATA DATA NULL NULL BIT 32 BIT 31 RECEIVER OPERATION t t SELEN t SELEN ENSEL t t ENEN D/REN t DATAEN ...
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... PL t CWSTR CWSTR EN1 EN2 / t CWHLD t CWSET DATA BUS Set CR1=1 Label #1 t ENDATA HI-3584 STATUS REGISTER READ CYCLE DON'T CARE t SELEN DATA VALID t ENDATA CONTROL REGISTER READ CYCLE DON'T CARE t SELEN DATA VALID t ENDATA LABEL MEMORY LOAD SEQUENCE Label #2 ...
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... BIT 32 RIN D D/R D/REN EN t SELEN SEL DON'T CARE t ENPL PL1 PL2 TXR ENTX 429DO 429DO HI-3584 TRANSMITTING DATA ARINC BIT ARINC BIT DATA DATA BIT 1 BIT 2 One Null Zero Null REPEATER OPERATION TIMING t END ENEN EN t ENSEL ...
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... Output Current: (Bi-directional Pins) Output Current: (All Other Outputs) Output Capacitance: Operating Supply Current VDD HI-3584 Power Dissipation at 25°C .......................................... 500 mW DC Current Drain per pin .............................................. ±10mA Storage Temperature Range ........................ -65°C to +150°C +0.3V DD Operating Temperature Range (Industrial): .... -40°C to +85°C °C for 10 seconds ° ...
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... Spacing - TX/R HIGH to ENTX LOW Delay - ENTX HIGH to TXAOUT or TXBOUT: High Speed Delay - ENTX HIGH to TXAOUT or TXBOUT: Low Speed REPEATER OPERATION TIMING Delay - TX/R LOW to ENTX HIGH MASTER RESET PULSE WIDTH ARINC DATA RATE AND BIT TIMING HI-3584 + SYMBOL Pulse Width - CWSTR t CWSTR ...
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... ADDITIONAL HI-3584 PIN CONFIGURATION (See page 1 for additional pin configurations) FF1 HF1 D/R2 FF2 HF2 SEL - 13 EN1 EN2 BD15 - 16 BD14 - 17 BD13 - 18 BD12 - 19 BD11 - 20 ORDERING INFORMATION HI - 3584 PART NUMBER No dash number PART NUMBER PART NUMBER PART NUMBER HI-3584 - N ENTX ...
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... PLASTIC QUAD FLAT PACK (PQFP) .520 ± .010 (13.2 ± .25) SQ. .063 ± .032 (1.6 ± .175) See Detail A .092 ± .004 (2.32 ± .12) HI-3584 PACKAGE DIMENSIONS .788 (20.0) MAX. SQ. .750 ± .007 (19.05 ± .18) .190 MAX. (4.826) ...
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... PLASTIC CHIP-SCALE PACKAGE 9.00 ± .10 9.00 ± .10 0.90 ± .10 HI-3584 PACKAGE DIMENSIONS Heat sink stud on bottom of package Heat sink must be left floating or connected to VDD DO NOT connect heat sink to GND 7.65 ± .15 0.40 ± .05 0.2 typ HOLT INTEGRATED CIRCUITS 15 millimeters 7.65 ± .15 0.50 0.25 typ ...