AM41DL3208G AMD [Advanced Micro Devices], AM41DL3208G Datasheet - Page 5

• Manufacturer Part Number: AM41DL3208G
• Description: 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) Static RAM
• Manufacturer: AMD [Advanced Micro Devices]

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Temporary Sector/Sector Block Unprotect ............................. 52
Alternate CE#f Controlled Erase and Program Operations .... 54
SRAM Read Cycle .................................................................. 56
SRAM Write Cycle .................................................................. 58
Figure 25. Temporary Sector/Sector Block Unprotect
Timing Diagram............................................................................... 52
Figure 26. Sector/Sector Block Protect and Unprotect
Timing Diagram............................................................................... 53
Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program) Op-
eration Timings................................................................................ 55
Figure 28. SRAM Read Cycle—Address Controlled....................... 56
Figure 29. SRAM Read Cycle ......................................................... 57
Figure 30. SRAM Write Cycle—WE# Control ................................. 58
Figure 31. SRAM Write Cycle—CE1#s Control .............................. 59
P R E L I M I N A R Y
Am41DL3208G
Flash Latchup Characteristics. . . . . . . . . . . . . . . 61
Package Pin Capacitance . . . . . . . . . . . . . . . . . . 61
Flash Data Retention . . . . . . . . . . . . . . . . . . . . . . 61
SRAM Data Retention . . . . . . . . . . . . . . . . . . . . . 62
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 63
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 64
Flash Erase And Programming Performance ........................ 61
FLB073—73-Ball Fine-Pitch Grid Array 8 x 11.6 mm ............. 63
Revision A (January 3, 2002) ................................................. 64
Figure 32. SRAM Write Cycle—UB#s and LB#s Control ............... 60
Figure 33. CE1#s Controlled Data Retention Mode....................... 62
Figure 34. CE2s Controlled Data Retention Mode......................... 62
February 13, 2002