AT52BC6402A-85CI ATMEL [ATMEL Corporation], AT52BC6402A-85CI Datasheet
AT52BC6402A-85CI
Related parts for AT52BC6402A-85CI
AT52BC6402A-85CI Summary of contents
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... V Operation CC • Access Time Stack Module Description The AT52BC6402A(T) consists of a 64-Mbit Flash stacked with a 16-Mbit PSRAM in a single CBGA package. Stack Module Memory Contents Device Memory Combination AT52BC6402A(T) 64M Flash + 16M PSRAM Flash/PSRAM Read Access ...
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... CBGA 66C4 – Top View Pin Configurations AT52BC6402A( A20 A11 A15 B A16 A8 A10 C WE A21 D PSGND RESET E WP VPP A19 PSOE G A18 A17 Pin Name Function A0 - A21 Address I/O0 - I/O15 Data Inputs/Outputs CE1 Flash Chip Enable ...
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... RESET pin halts the present device operation and puts the outputs of the device in a high-impedance state. When a high level is reasserted on the RESET pin, the device returns to read or standby mode, depending upon the state of the control pins. AT52BC6402A(T) input. Erase, Erase Suspend/Resume, Program Sus- is ...
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... AT52BC6402A(T) 4 ERASE: Before a word can be reprogrammed it must be erased. The erased state of the memory bits is a logical “1”. The entire memory can be erased by using the Chip Erase command or individual planes or sectors can be erased by using the Plane Erase or Sector Erase commands. CHIP ERASE: Chip Erase is a six-bus cycle operation. The automatic erase begins on the rising edge of the last WE pulse ...
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... IL [110 [100] Note: 1. The notation [ denotes the locking state of a sector. The current locking state of a sector is defined by the state of WP and the two bits of the sector-lock status D[1:0]. AT52BC6402A(T) Erase/ Prog Allowed? Comments 0 Yes No sector is locked 1 No Sector is Softlocked. The Unlock command can unlock the sector ...
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... AT52BC6402A(T) 6 SECTOR PROTECTION DETECTION: A software method is available to determine if the sector protection Softlock or Hardlock features are enabled. When the device is in the software product identification mode (see Software Product Identification Entry and Exit sections) a read from the I/O0 and I/O1 at address location 00002H within a sector will show if the sector is unlocked, softlocked, or hardlocked ...
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... The program suspend and resume are one-bus cycle commands. The command sequence for the erase suspend and program suspend are the same, and the command sequence for the erase resume and program resume are the same. AT52BC6402A(T) PP status bit has been set to a “1”, ...
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... AT52BC6402A(T) 8 128-BIT PROTECTION REGISTER: The 64-Mbit device contains a 128-bit register that can be used for security purposes in system design. The protection register is divided into two 64-bit blocks. The two blocks are designated as block A and block B. The data in block A is non-changeable and is programmed at the factory with a unique number. ...
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... I/O7 should be rechecked even if I/O5 = “1” because I/O7 may change simultaneously with I/O5. 3441B–STKD–11/04 Figure 3. Data Polling Algorithm (Configuration Register = 01) YES Note: Program/Erase Operation Successful, Device in Read Mode AT52BC6402A(T) START Read I/O7 - I/O0 Addr = YES NO I/O3, I/ YES Program/Erase Program/Erase Operation Operation Not ...
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... Program/Erase Operation Not Successful, Write Product ID Exit Command Note: 1. The system should recheck the toggle bit even if I/O5 = “1” because the toggle bit may stop toggling as I/O5 changes to “1”. AT52BC6402A(T) 10 Figure 5. Toggle Bit Algorithm (Configuration Register = 01) NO Program/Erase Operation Successful, Device in ...
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... DATA TOGGLE 0/0 DATA DATA DATA DATA DATA DATA TOGGLE DATA DATA DATA TOGGLE DATA DATA DATA TOGGLE I/O7/0 DATA DATA AT52BC6402A(T) 00/01 00/01 00/01 00/01 Plane C Plane D Plane A Plane B DATA DATA 1 DATA DATA DATA DATA 1 DATA DATA DATA DATA TOGGLE DATA DATA DATA DATA ...
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... Any address within the user programmable register region. Please see “Protection Register Addressing Table” on page 13. 12. For the AT49BV6416, xxxx = 0000H. For the AT49BV6416T, xxxx = 3F80H. 13. For the AT49BV6416, xxxx = 0000H. For the AT49BV6416T, xxxx = 0F80H. AT52BC6402A(T) 12 (1) 1st Bus ...
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... AT52BC6402A(T) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied ...
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... SA38 32K B SA39 32K B SA40 32K B SA41 32K B SA42 32K B SA43 32K B SA44 32K AT52BC6402A(T) 14 Memory Organization – 64-Mbit Bottom Boot (Continued) x16 Address Range Plane (A21 - A0) B 00000 - 00FFF B 01000 - 01FFF B 02000 - 02FFF B 03000 - 03FFF B 04000 - 04FFF B 05000 - 05FFF B 06000 - 06FFF ...
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... D 310000 - 317FFF D 318000 - 31FFFF D 320000 - 327FFF D 328000 - 32FFFF D D 330000 - 337FFF 338000 - 33FFFF D 340000 - 347FFF D 348000 - 34FFFF AT52BC6402A(T) x16 Size Address Range Sector (Words) (A21 - A0) SA113 32K 350000 - 357FFF SA114 32K 358000 - 35FFFF SA115 32K 360000 - 367FFF SA116 32K ...
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... SA38 32K C SA39 32K C SA40 32K C SA41 32K C SA42 32K C SA43 32K C SA44 32K AT52BC6402A(T) 16 Memory Organization – 64-Mbit Top Boot (Continued) x16 Address Range Plane (A21 - A0) C 00000 - 07FFF C 08000 - 0FFFF C 10000 - 17FFF C 18000 - 1FFFF C 20000 - 27FFF C 28000 - 2FFFF C 30000 - 37FFF ...
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... A 340000 - 347FFF A 348000 - 34FFFF A 350000 - 357FFF A 358000 - 35FFFF A 360000 - 367FFF A 368000 - 36FFFF A 370000 - 377FFF A 378000 - 37FFFF 380000 - 387FFF AT52BC6402A(T) x16 Size Address Range Sector (Words) (A21 - A0) SA113 32K 388000 - 38FFFF SA114 32K 390000 - 397FFF SA115 32K 398000 - 39FFFF SA116 32K ...
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... X can Refer to AC programming waveforms. 3. Manufacturer Code: 001FH; Device Code: 00D6H – Bottom Boot; 00D2H – Top Boot. 4. The VPP pin can be tied (min) = 1.65V. IHPP 6. V (max) = 0.8V. ILPP AT52BC6402A(T) 18 Industrial (4) WE RESET ...
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... OUT -100 µ -400 µA OH 2.0V AC DRIVING 1.5V LEVELS 0. < 1.8K OUTPUT PIN 1. Max Units 6 12 AT52BC6402A(T) Min Max 0.6 2.0 0.45 2.5 2.4 AC MEASUREMENT LEVEL Conditions OUT Units µA µA µ ...
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... DF t RESET to Output Delay RO Asynchronous Read Cycle Waveform Notes may be delayed may be delayed without impact ACC specified from OE or CE, whichever occurs first ( pF). DF AT52BC6402A(T) 20 64-Mbit-70 Min Max 150 (1)(2)(3) tRC A0 - A21 ADDRESS VALID ...
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... High Pulse Width WPH AC Word Load Waveforms WE Controlled CE I/O0-I/O15 A0 -A21 WE CE Controlled WE I/O0-I/O15 A0 -A21 CE 3441B–STKD–11/04 DATA VALID DATA VALID AT52BC6402A(T) Min Max Units ...
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... Command Definitions on page 12.) 3. For chip erase, the data should be XX10H, for plane erase, the data should be XX20H, and for sector erase, the data should be XX30H 4. The waveforms shown above use the WE controlled AC Word Load Waveforms. AT52BC6402A( ...
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... OEHP 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary. 3441B–STKD–11/04 Min 10 10 (2) 0 (1) Min AT52BC6402A(T) Typ Max Typ Max Units Units ...
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... AT52BC6402A(T) 24 Comments “Q” “R” “Y” VCC min write/erase VCC max write/erase VPP min voltage VPP max voltage Typ word write – 16 µs Typ block erase – 500 ms ...
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... Bit 0 – 4 word page, 0 – no, 1 – yes Bit 1 – 8 word page, 0 – no, 1 – yes Undefined bits are “0” Location of protection register lock byte, the section's first byte # of bytes in the factory prog section of prot register – 2 bytes in the user prog section of prot register – 2*n AT52BC6402A(T) 25 ...
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... PSRAM Description Features Block Diagram AT52BC6402A(T) 26 The device is a 16-Mbit 1T/1C PSRAM featured by high-speed operation and super low power consumption. The 16-Mbit device adopts one transistor memory cell and is orga- nized as 1,048,576 words by 16 bits. It operates in the extended range of temperatures and supports a wide operating voltage range. The device also supports the deep power- down mode for a super low standby current. • ...
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... Upper Byte Read L L Word Read L H Lower Byte Write H L Upper Byte Write L L Word Write Min 2.7 0 2.2 (1) -0.3 AT52BC6402A(T) Rating Unit +0.3 CC 1.0 °C•sec 260•10 I/O Pin I/O1 ~ I/O8 I/O9 ~ I/O16 High-Z High-Z High-Z High-Z Deep Power-down High-Z High-Z High-Z High-Z D High-Z OUT ...
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... OH (1) Capacitance (Temp = 25° 1.0 MHz) Symbol Parameter C Input Capacitance (Add, CS1, CS2, IN PSWE, PSOE, UB, LB) C Output Capacitance (I/O) OUT Note: 1. These parameters are sampled and not 100% tested. AT52BC6402A(T) 28 Test Condition GND < V < GND < V < OUT CC CS1 = V , CS2 = ...
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... Output Active from End of Write OW AC Test Conditions T = -30°C to 85°C (M), Unless Otherwise Specified A Parameter Input Pulse Level Input Rising and Fall Time Input and Output Timing Reference Level Output Load 3441B–STKD–11/04 AT52BC6402A( Min Max ...
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... AC Test Loads Power-up Sequence Deep Power-down Entry Sequence Deep Power-down Exit Sequence State Diagram AT52BC6402A( OUT Ohm 0 Note: Including jig and scope capacitance. 1. Supply power. 2. Maintain stable power for longer than 200 µs. 1. Keep CS2 low state. Deep Power-down mode is maintained while CS2 is low state ...
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... CS2 IDPD 3441B–STKD–11/04 Wait 200 µs reaches specified minimum level. In case of CS2 is switched from CC reached specified level defined as the deep power-down exit. CC Deep Power-down Mode Standby Mode Deep Power-down Mode AT52BC6402A(T) Normal Operation Wait 200 µs Normal Operation 31 ...
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... CHZ BHZ OHZ are defined as the time at which the outputs achieve the low impedance state. These are not referenced to output voltage levels. 4. CS1 in high for the standby, low for active. AT52BC6402A( ...
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... Do not input data to the I/O pins while they are in the output state. 3441B–STKD–11/04 (1),(4),(5),(9),(10 (3)(8) t WHZ (1),(4),(5),(9),(10 AT52BC6402A(T) ( DATA VALID t OW (6) ( DATA VALID (7) 33 ...
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... ADDRESS CS1 CS2 V IH UB, LB PSWE HIGH-Z DATA IN Notes: 1. The t is specified from the time satisfied both Although UB and LB are high state, it’s illegal function to change address both CS and PSWE are in low state. AT52BC6402A( ...
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... Avoidable Timing(1) or toggle the CS1 to high (> t time at least which showed in Avoidable Timing(2) > 48 µs < > 48 µs > > 48 µs < AT52BC6402A(T) during over 48 µs at read RC ) one RC > ...
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... Ordering Information t ACC (ns) Ordering Code AT52BC6402A-70CI 70 AT52BC6402AT-70CI AT52BC6402A-85CI 85 AT52BC6402AT-85CI 66C6 66-ball, Plastic Chip-size Ball Grid Array Package (CBGA) AT52BC6402A(T) 36 Flash Boot Block PSRAM Bottom Top Bottom Top Package Type Package Operation Range Industrial 66C6 (-40° to 85°C) ...
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... D1 A1 Ball Corner 1.20 REF Øb TITLE 66C6, 66-ball ( Array 1.0 mm Body, 0.8 mm Ball Pitch Chip-scale Ball Grid Array Package (CBGA) AT52BC6402A(T) 0. Seating Plane Side View A1 A COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM A – – ...
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Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 ...