AM41DL6408H8H70IS AMD [Advanced Micro Devices], AM41DL6408H8H70IS Datasheet - Page 58

• Manufacturer Part Number: AM41DL6408H8H70IS
• Description: Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
• Manufacturer: AMD [Advanced Micro Devices]

AC CHARACTERISTICS
SRAM Write Cycle
Notes:
1. WE# controlled, if CIOs is low, ignore UB#s and LB#s timing.
2. t
3. t
4. t
5. A write occurs during the overlap (t
56
asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A
write ends at the earliest transition when CE1#s goes high and WE# goes high. The t
to the end of write.
CW
WR
AS
Parameter
Symbol
is measured from the address valid to the beginning of write.
is measured from CE1#s going low to the end of write.
is measured from the end of write to the address change. t
t
t
t
t
t
t
t
Address
CE1#s
CE2s
WE#
Data In
Data Out
t
t
WHZ
t
t
WC
BW
WP
WR
DW
OW
Cw
AW
DH
AS
Description
Write Cycle Time
Chip Enable to End of Write
Address Setup Time
Address Valid to End of Write
UB#s, LB#s to End of Write
Write Pulse Time
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
A D V A N C E
Figure 31. SRAM Write Cycle—WE# Control
WP
Data Undefined
) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when
High-Z
(See Note 3)
t
AS
Am41DL6408H
I N F O R M A T I O N
Max
t
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
min
WHZ
(See Note 1)
(See Note 1)
WR
t
AW
applied in case a write ends as CE1#s or WE# going high.
(See Note 4)
t
WC
t
t
CW
CW
t
WP
71
55
45
45
45
40
25
t
DW
Data Valid
20
WP
Speed
is measured from the beginning of write
70
70
60
60
60
50
30
0
0
0
0
5
t
DH
t
t
WR
OW
85
85
70
70
70
60
25
35
High-Z
November 24, 2003
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns