AM49DL640BG25IS SPANSION [SPANSION], AM49DL640BG25IS Datasheet - Page 9

• Manufacturer Part Number: AM49DL640BG25IS
• Description: Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
• Manufacturer: SPANSION [SPANSION]

PIN DESCRIPTION
A20–A0
A21, A-1
DQ15–DQ0
CE#f
CE1#s
CE2s
OE#
WE#
RY/BY#
UB#s
LB#s
CIOf
RESET#
WP#/ACC
V
V
V
NC
8
CC
CC
SS
f
s
= 21 Address Inputs (Common)
= 2 Address Inputs (Flash)
= 16 Data Inputs/Outputs (Common)
= Chip Enable (Flash)
= Chip Enable 1 (pSRAM)
= Chip Enable 2 (pSRAM)
= Output Enable (Common)
= Write Enable (Common)
= Ready/Busy Output
= Upper Byte Control (pSRAM)
= Lower Byte Control (pSRAM)
= I/O Configuration (Flash)
= Hardware Reset Pin, Active Low
= Hardware Write Protect/
= Flash 3.0 volt-only single power sup-
= pSRAM Power Supply
= Device Ground (Common)
= Pin Not Connected Internally
CIOf = V
CIOf = V
Acceleration Pin (Flash)
ply (see Product Selector Guide for
speed options and voltage supply
tolerances)
IH
IL
= Byte mode (x8)
= Word mode (x16),
P R E L I M I N A R Y
Am49DL640BG
LOGIC SYMBOL
21
A21, A-1
SA
CE#f
CE1#s
CE2s
OE#
WE#
WP#/ACC
RESET#
UB#s
LB#s
CIOf
A20–A0
DQ15–DQ0
RY/BY#
16 or 8
March 8, 2002