K4D263238M-QC45 SAMSUNG [Samsung semiconductor], K4D263238M-QC45 Datasheet
![no-image](/images/no-image-200.jpg)
K4D263238M-QC45
Related parts for K4D263238M-QC45
K4D263238M-QC45 Summary of contents
Page 1
... K4D263238M 128Mbit DDR SDRAM Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL Samsung Electronics reserves the right to change products or specification without notice 32Bit x 4 Banks Revision 1.3 August 2001 - 1 - 128M DDR SDRAM Rev. 1.3 (Aug. 2001) ...
Page 2
... The specification for the 222MHz/250MHz is preliminary one. Revision 1.1 (March 5, 2000) • Added K4D263238M-QC40 with VDD&VDDQ=2.8V • Changed VDD/VDDQ of K4D263238M-QC45 from 2.5V to 2.8V. Accordingly, DC current characteristics values have been changed. - Changed CAS latency of K4D263238M-QC45 from CL4 to CL3. • Changed tWPREH of K4D263238M-QC50 from 0.3tCK to 0.25tCK ...
Page 3
... OUT Revision 0.4 (November 29, 2000) - Preliminary • Removed K4D263238M-QC40 • Several AC parameters of K4D263238M-QC45 have been changed - Changed tDQSQ from 0.4ns to 0.45ns. Changed tQH from tHP-0.6ns to tHP-0.45ns. - Changed tDQSCK & tAC from 0.6ns to 0.7ns - Changed tDQSS from 0.75tCK/1.25tCK to 0.8tCK/1.2tCK. Accordingly, changed tWPREH from 0.25tCK to 0.3tCK. ...
Page 4
... All inputs except data & DM are sampled at the positive going edge of the system clock • Differential clock input • No Write Interrupted by Read function ORDERING INFORMATION Part NO. K4D263238M-QC45 K4D263238M-QC50 K4D263238M-QC55 K4D263238M-QC60 GENERAL DESCRIPTION FOR 1M x 32Bit x 4 Bank DDR SDRAM The K4D263238 is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized 1,048,576 words by 32 bits, fabricated with SAMSUNG s high performance CMOS technology ...
Page 5
... K4D263238M PIN CONFIGURATION 81 DQ29 VSSQ 82 DQ30 83 84 DQ31 VSS 85 86 VDDQ N N.C N N.C 91 N.C VSSQ 92 93 RFU DQS 94 95 VDDQ VDD 96 97 DQ0 DQ1 98 VSSQ 99 100 DQ2 PIN DESCRIPTION CK,CK Differential Clock Input CKE Clock Enable CS Chip Select RAS Row Address Strobe CAS ...
Page 6
... K4D263238M INPUT/OUTPUT FUNCTIONAL DESCRIPTION Symbol *1 Input CK, CK CKE Input CS Input RAS Input CAS Input WE Input DQS Input/Output Input Input/Output Input Input Power Supply Power Supply DDQ SSQ V Power Supply REF ...
Page 7
... K4D263238M BLOCK DIAGRAM (1Mbit x 32I Bank) Bank Select CK,CK ADDR LCKE LRAS LCBR CK,CK CKE 32 Intput Buffer CK, CK Data Input Register Serial to parallel 64 1Mx32 1Mx32 1Mx32 1Mx32 Column Decoder Latency & Burst Length Programming Register LWE LCAS LWCBR Timing Register CS RAS CAS ...
Page 8
... K4D263238M FUNCTIONAL DESCRIPTION • Power-Up Sequence DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. 1. Apply power and keep CKE at low state (All other inputs may be undefined) - Apply VDD before VDDQ . - Apply VDDQ before VREF & VTT 2. Start clock and maintain stable condition for minimum 200us. ...
Page 9
... K4D263238M MODE REGISTER SET(MRS) The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for proper operation ...
Page 10
... K4D263238M EXTENDED MODE REGISTER SET(EMRS) The extended mode register stores the data for enabling or disabling DLL and selecting output driver strength. The default value of the extended mode register is not defined, therefore the extend mode register must be written after power up for enabling or disabling DLL. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register) ...
Page 11
... K4D263238M ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Voltage on V supply relative to Vss DD Voltage on V supply relative to Vss DD Storage temperature Power dissipation Short circuit current Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. ...
Page 12
... K4D263238M DC CHARACTERISTICS Recommended operating conditions Unless Otherwise Noted, T Sym- Parameter bol Operating Current I CC1 (One Bank Active) Precharge Standby Current I CC2 in Power-down mode Precharge Standby Current I CC2 in Non Power-down mode Active Standby Current I CC3 power-down mode Active Standby Current in I CC3 ...
Page 13
... K4D263238M AC OPERATING TEST CONDITIONS Parameter Input reference voltage for CK(for single ended) CK and CK signal maximum peak swing CK signal minimum slew rate Input Levels Input timing measurement reference level Output timing measurement reference level Output load condition Output CAPACITANCE (V =2.5V Parameter ...
Page 14
... K4D263238M AC CHARACTERISTICS Parameter Symbol CL cycle time CK CL high level width low level width CL t DQS out access time from CK DQSCK t Output access time from Data strobe edge to Dout edge DQSQ t Read preamble RPRE t Read postamble RPST valid DQS-in ...
Page 15
... K4D263238M Note The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data strobe and all data associated with that data strobe are coincidentally valid. - The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst case ...
Page 16
... K4D263238M AC CHARACTERISTICS (I) Parameter Symbol Row cycle time Refresh row cycle time RFC t Row active time RAS t RAS to CAS delay for Read RCDRD t RAS to CAS delay for Write RCDWR t Row precharge time RP t Row active to Row active RRD t Last data in to Row precharge ...
Page 17
... K4D263238M AC CHARACTERISTICS (II) K4D263238M-QC45* Frequency Cas Latency 222MHz ( 4.5ns ) 4 200MHz ( 5.0ns ) 3 183MHz ( 5.5ns ) 3 166MHz ( 6.0ns ) 3 143MHz ( 7.0ns ) 3 K4D263238M-QC50 Frequency Cas Latency 200MHz ( 5.0ns ) 3 183MHz ( 5.5ns ) 3 166MHz ( 6.0ns ) 3 143MHz ( 7.0ns ) 3 K4D263238M-QC55 Frequency Cas Latency 183MHz ( 5.5ns ) 3 166MHz ( 6.0ns ) 3 143MHz ( 7.0ns ) 3 K4D263238M-QC60 Frequency Cas Latency 166MHz ( 6 ...
Page 18
... K4D263238M Simplified Timing(2) @ BL=4, CL CK, CK BA[1:0] BAa BAa Ra Ra A8/AP ADDR Ra Ca (A0~A7, A9~,A11) WE DQS Da0 Da1 Da2 Da3 DQ DM ACTIVEA WRITEA COMMAND tRCD tRAS Normal Write Burst (@ BL= BAa BAa Ra Ra PRECH ACTIVEA tRP tRC tRRD Multi Bank Interleaving Write Burst ...
Page 19
... K4D263238M PACKAGE DIMENSIONS (TQFP) #100 #1 0.825 17.20 0.20 14.00 0.10 23.20 0.20 20.00 0.10 0.30 0.65 0.08 0.13 MAX 1.00 0.10 1.20 MAX * 0.10 MAX 0.05 MIN 0.80 0. 128M DDR SDRAM Dimensions in Millimeters 0.09~0.20 Rev. 1.3 (Aug. 2001) ...