AM49PDL127BH66IS SPANSION [SPANSION], AM49PDL127BH66IS Datasheet - Page 11
AM49PDL127BH66IS
Manufacturer Part Number
AM49PDL127BH66IS
Description
128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 32 Mbit (2 M x 16-Bit) CMOS
Manufacturer
SPANSION [SPANSION]
Datasheet
1.AM49PDL127BH66IS.pdf
(86 pages)
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PIN DESCRIPTION
A20–A0
A21
A22
DQ15–DQ0
CE#f1
CE#f2
CE#1ps
CE2ps
OE#
WE#
RY/BY#
UB#s
LB#s
RESET#
WP#/ACC
V
V
V
NC
December 16, 2003
CC
CC
SS
f
s
= Output Enable (Common)
= Ready/Busy Output and open drain.
= 21 Address Inputs (Common)
= Address Inputs (Flash)
= Address Input (PDL127 only)
= 16 Data Inputs/Outputs (Common)
= Chip Enable 1 (Flash)
= Chip Enable 2 (Flash)
= Chip Enable 1 (pSRAM)
= Chip Enable 2 (pSRAM)
= Write Enable (Common)
= Upper Byte Control (pSRAM)
= Lower Byte Control (pSRAM)
= Hardware Reset Pin, Active Low
= Write Protect/Acceleration Input.
= Flash 3.0 volt-only single power sup-
= pSRAM Power Supply
= Device Ground (Common)
= Pin Not Connected Internally
(Flash)
(PDL 129 only)
When RY/BY# = V
ready to accept read operations and
commands. When RY/BY# = V
the device is either executing an em-
bedded algorithm or the device is
executing a hardware reset opera-
tion.
When WP/ACC#= V
and lowest two 4K-word sectors are
write protected regardless of other
sector protection configurations.
When WP/ACC#= V
are unprotected unless the DYB or
PPB is programmed. When
WP/ACC#= 12V, program and erase
operations are accelerated.
ply (see Product Selector Guide for
speed options and voltage supply
tolerances)
A D V A N C E
IH
, the device is
IL
IH
Am49PDL127BH/Am49PDL129BH
, the highest
, these sector
OL
,
I N F O R M A T I O N
LOGIC SYMBOL
21
CE#f2 (PDL129 Only)
A22 (PDL127 Only)
CE2ps
CE#f1
CE#1ps
OE#
WE#
WP#/ACC
RESET#
UB#s
LB#s
A21
A20–A0
DQ15–DQ0
RY/BY#
16
9
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