K4S510732B-TC1H SAMSUNG [Samsung semiconductor], K4S510732B-TC1H Datasheet - Page 3

• Manufacturer Part Number: K4S510732B-TC1H
• Description: Stacked 512Mbit SDRAM
• Manufacturer: SAMSUNG [Samsung semiconductor]

16M x 8Bit x 4 Banks Synchronous DRAM
FEATURES
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
• All inputs are sampled at the positive going edge of the system
• Burst read single-bit write operation
• DQM for masking
• Auto & self refresh
• 64ms refresh period (8K Cycle)
K4S510732B
FUNCTIONAL BLOCK DIAGRAM
clock.
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
/CS1,CKE1
/CS0,CKE0
CLK,CAS,RAS
/WE,DQM
*
Staktek’ s stacking technology is Samsung’ s stacking technology of choice.
Samsung Electronics reserves the right to change products or specification without notice.
GENERAL DESCRIPTION
The K4S510732B is 536,870,912 bits synchronous high data rate
Dynamic RAM organized as 4 x 16,777,216 words by 8 bits, fabri-
cated with SAMSUNG's high performance CMOS technology. Syn-
chronous design allows precise cycle control with the use of
system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and
programmable latencies allow the same device to be useful for a
variety of high bandwidth, high performance memory system appli-
cations.
ORDERING INFORMATION
DQ0 ~ DQ7
K4S510732B-TC/L75
K4S510732B-TC/L1H
K4S510732B-TC/L1L
32Mx8
32Mx8
Part No.
A0~A12,BA0,BA1
133MHz(CL=3)
100MHz(CL=2)
100MHz(CL=3)
Max Freq.
Rev. 0.0 Feb.2001
CMOS SDRAM
Preliminary
Interface
LVTTL
Package
TSOP(II)
54pin