K4H510838B-N SAMSUNG [Samsung semiconductor], K4H510838B-N Datasheet - Page 4

• Manufacturer Part Number: K4H510838B-N
• Description: 512Mb B-die DDR SDRAM Specification 54 sTSOP-II (400mil x 441mil)
• Manufacturer: SAMSUNG [Samsung semiconductor]

1.0 Key Features
2.0 Ordering Information
3.0 Operating Frequencies
DDR SDRAM 512Mb B-die (x8)
• VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333
• VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe [DQS] (x4,x8)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• DM for write masking only (x4, x8)
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
• Maximum burst refresh cycle : 8
• 54pin sTSOP(II)-400
Note : Leaded and Lead-free(Pb-free) can be discriminated by PKG P/N (N : 54 sTSOP with Leaded, V : 54 sTSOP with Lead-free)
-. Read latency : DDR266(2, 2.5 Clock), DDR333(2.5 Clock), DDR400(3 Clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
K4H510838B-N(V)C/LCC
Speed @CL2.5
K4H510838B-N(V)C/LB3
K4H510838B-N(V)C/LA2
K4H510838B-N(V)C/LB0
CL-tRCD-tRP
Speed @CL2
Speed @CL3
Part No.
(Leaded & Pb-Free(RoHS compliant))
CC(DDR400@CL=3)
166MHz
200MHz
3-3-3
-
64M x 8
Org.
B3(DDR333@CL=2.5)
CC(DDR400@CL=3)
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
133MHz
166MHz
2.5-3-3
Max Freq.
-
package
A2(DDR266@CL=2.0)
133MHz
133MHz
2-3-3
Interface
-
SSTL2
Rev. 1.3 June. 2005
B0(DDR266@CL=2.5)
DDR SDRAM
54pin sTSOP II
100MHz
133MHz
2.5-3-3
Package
-