SSD1828Z ETC [List of Unclassifed Manufacturers], SSD1828Z Datasheet - Page 17

• Manufacturer Part Number: SSD1828Z
• Description: LCD Segment / Common Driver with Controller CMOS
• Manufacturer: ETC [List of Unclassifed Manufacturers]

12
SSD1828
7.4
7.5
7.6
7.7
Table 5 -Modes of Operation
MPU Serial 4-wire Interface
The serial interface consists of serial clock SCK, serial data SDA, D/C and CS#. SDA is shifted
into a 8-bit shift register on every rising edge of SCK in the order of D
sampled on every eighth clock and the data byte in the shift register is written to the Display
Data RAM or command register in the same clock. No extra clock or command is required to
end the transmission.
MPU Serial 3-wire interface
Operation is similar to 4-wire serial interface while D/C is not been used. The Display Data
Length instruction is used to indicate that a specified number display data byte(s) (1-256) are to
be transmitted. Next byte after the display data string is handled as a command.
It should be noted that if there is a signal glitch at SCK that causing an out of synchronization in
the serial communication, a hardware reset pulse at RES# pin is required to initialize the chip
for re-synchronization.
Graphic Display Data RAM (GDDRAM)
size of the RAM is 96 x 65 = 6,240bits for SSD1828. Figure 5 is a description of the GDDRAM
address map.
provided.
set to control the portion of the RAM data mapped to the display. Figure 5 shows the case in
which the display start line register is set at 30H.
either preparation of vertical scrolling data or even for the system usage.
Oscillator Circuit
This module is an On-Chip low power RC oscillator circuitry (Figure 4). The oscillator generates
the clock for the DC-DC voltage converter. This clock is also used in the Display Timing
Generator.
Data Read
Data Write
Command Read
Command Write
The GDDRAM is a bit mapped static RAM holding the bit pattern to be displayed. The
For mechanical flexibility, re-mapping on both Segment and Common outputs are
For vertical scrolling of display, an internal register storing the display start line can be
For those GDDRAM out of the display common range, they could still be accessed, for
Rev 1.10
07/2002
6800 Parallel
Status only
Yes
Yes
Yes
8080 Parallel
Status only
Yes
Yes
Yes
Serial
Yes
Yes
No
No
7
, D
6
, ... D
0
. D/C is
SOLOMON