MT8LSDT3264AG-133 MICRON [Micron Technology], MT8LSDT3264AG-133 Datasheet - Page 11

• Manufacturer Part Number: MT8LSDT3264AG-133
• Description: SYNCHRONOUS DRAM MODULE
• Manufacturer: MICRON [Micron Technology]

Commands
able commands. This is followed by written descrip-
tion of each command. For a more detailed descrip-
Table 9:
CKE is HIGH for all commands shown except SELF REFRESH; notes appear following the Truth Table
NOTE:
32,64 Meg x 64 SDRAM DIMMs
SD8_16C32_64x64AG_C.fm - Rev. C 11/02
1. A0–A12 provide row address; BA0–BA1 determine which device bank is made active.
2. A0–A9 provide column address; A10 HIGH enables the auto-precharge feature (nonpersistent), while A10 LOW dis-
3. A10 LOW: BA0–BA1 determine which device bank is being precharged. A10 HIGH: all device banks are precharged
4. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
5. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
6. A0–A11 define the op-code written to the mode register and A12 should be driven LOW.
7. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).
NAME (FUNCTION)
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE
burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
LOAD MODE REGISTER
Write Enable/Output Enable
Write Inhibit/Output High-Z
The Truth Table provides a quick reference of avail-
ables the auto-precharge feature; BA0-BA1 determine which device bank is being read from or written to.
and BA0, BA1 are “Don’t Care.”
Truth Table – SDRAM Commands and DQMB Operation
CS#
H
L
L
L
L
L
L
L
L
–
–
11
RAS# CAS# WE# DQMB
tion of commands and operations, refer to the 256Mb
SDRAM component data sheet.
X
H
H
H
H
L
L
L
L
–
–
Micron Technology, Inc., reserves the right to change products or specifications without notice.
X
H
H
H
H
L
L
L
L
–
–
X
H
H
H
H
L
L
L
L
–
–
168-PIN SDRAM DIMMs
256MB / 512MB (x64)
L/H
L/H
H
X
X
X
X
X
X
X
L
Bank/Row
Bank/Col
Bank/Col
Op-code
ADDR
Code
X
X
X
X
–
–
High-Z
Active
Active
©2002, Micron Technology Inc.
Valid
DQ
X
X
X
X
X
X
X
NOTES
4, 5
1
2
2
3
6
7
7