M368L1624FTM-CB3AA SANKEN [Sanken electric], M368L1624FTM-CB3AA Datasheet - Page 15
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M368L1624FTM-CB3AA
Manufacturer Part Number
M368L1624FTM-CB3AA
Description
184pin Unbuffered Module based on 256Mb F-die with 64/72-bit Non-ECC / ECC
Manufacturer
SANKEN [Sanken electric]
Datasheet
1.M368L1624FTM-CB3AA.pdf
(25 pages)
AC Timming Parameters & Specifications
256MB, 512MB Unbuffered DIMM
Row cycle time
Refresh row cycle time
Row active time
RAS to CAS delay
Row precharge time
Row active to Row active delay
Write recovery time
Last data in to Read command
Col. address to Col. address delay
Clock cycle time
Clock high level width
Clock low level width
DQS-out access time from CK/CK
Output data access time from CK/CK
Data strobe edge to ouput data edge
Read Preamble
Read Postamble
CK to valid DQS-in
DQS-in setup time
DQS-in hold time
DQS falling edge to CK rising-setup time
DQS falling edge from CK rising-hold time
DQS-in high level width
DQS-in low level width
DQS-in cycle time
Address and Control Input setup time(fast)
Address and Control Input hold time(fast)
Address and Control Input setup time(slow)
Address and Control Input hold time(slow)
Data-out high impedence time from CK/CK
Data-out low impedence time from CK/CK
Output Slew Rate Matching Ratio(rise to fall)
Parameter
CL=2.0
CL=2.5
Symbol
tWPRES
tDQSCK
tDQSQ
tWPRE
tDQSH
tRPRE
tDQSS
tDQSL
tSLMR
tRPST
tRCD
tWTR
tCCD
tRFC
tRAS
tRRD
tDSS
tDSH
tDSC
tWR
tRC
tRP
tCK
tCH
tAC
tHZ
tCL
tLZ
tIS
tIH
tIS
tIH
(DDR333@CL=2.5)
Min
0.45
0.45
0.75
0.25
0.35
0.35
0.75
0.75
0.67
-0.6
-0.7
-0.7
7.5
0.9
0.4
0.2
0.2
0.9
0.8
0.8
60
72
42
18
18
12
15
1
1
6
0
-
B3
Max
+0.7
+0.7
+0.7
0.55
0.55
+0.6
0.45
1.25
70K
1.1
0.6
1.1
1.5
12
12
(DDR266@CL=2.0
-0.75
-0.75
-0.75
0.45
0.45
0.75
0.25
0.35
0.35
0.67
7.5
7.5
0.9
0.4
0.2
0.2
0.9
0.9
0.9
1.0
1.0
60
75
45
15
15
15
15
1
1
0
-
AA
+0.75
+0.75
120K
+0.75
+0.75
0.55
0.55
1.25
0.5
1.1
0.6
1.1
1.5
12
12
(DDR266@CL=2.0)
-0.75
-0.75
-0.75
Min
0.45
0.45
0.75
0.25
0.35
0.35
0.67
7.5
7.5
0.9
0.4
0.2
0.2
0.9
0.9
0.9
1.0
1.0
75
65
45
20
20
15
15
1
1
0
-
A2
+0.75
+0.75
120K
+0.75
+0.75
Max
0.55
0.55
1.25
0.5
1.1
0.6
1.1
1.5
12
12
(DDR266@CL=2.5) Unit
-0.75
-0.75
-0.75
Min
0.45
0.45
0.75
0.25
0.35
0.35
0.67
Rev. 1.2 May, 2004
7.5
0.9
0.4
0.2
0.2
0.9
0.9
0.9
1.0
1.0
75
65
45
20
20
15
15
10
1
1
0
-
B0
DDR SDRAM
+0.75
+0.75
120K
+0.75
+0.75
Max
0.55
0.55
1.25
0.5
1.1
0.6
1.1
1.5
12
12
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
i,5.7~9
i,5.7~9
Note
i, 6~9
i, 6~9
12
3
1
1