M391B1G73BH0 SAMSUNG [Samsung semiconductor], M391B1G73BH0 Datasheet
M391B1G73BH0
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M391B1G73BH0 Summary of contents
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... For updates or additional information about Samsung products, contact your nearest Samsung office. All brand names, trademarks and registered trademarks belong to their respective owners. ⓒ 2012 Samsung Electronics Co., Ltd. All rights reserved Rev. 1.3, May. 2012 M378B5173BH0 M378B1G73BH0 M391B1G73BH0 ...
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... Revision History Revision No. 1.0 - First SPEC. Release 1.1 - Changed timing parameters(Setup/Hold time) 1.2 - Changed Input/Output Capacitance on page 23 - Corrected Typo 1.21 - Corrected Typo (tCKmin) 1.3 - Added Module line up (4GB NON ECC UDIMM) - Added IDD(1866Mbps) values datasheet History - 2 - Rev. 1.3 DDR3 SDRAM Draft Date Remark Editor May. 2011 - J.Y.Lee Jul ...
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... DRAM Pin Wiring Mirroring .............................................................................................................................. 9 9. Function Block Diagram: ............................................................................................................................................... 10 9.1 4GB, 512Mx64 Non ECC Module (Populated as 1 rank of x8 DDR3 SDRAMs) ..................................................... 10 9.2 8GB, 1Gx64 Non ECC Module (Populated as 2 ranks of x8 DDR3 SDRAMs) ....................................................... 11 9.3 8GB, 1Gx72 ECC Module (Populated as 2 ranks of x8 DDR3 SDRAMs) ............................................................... 12 10. Absolute Maximum Ratings ........................................................................................................................................ 13 10 ...
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... Unbuffered DIMM 1. DDR3 Unbuffered DIMM Ordering Information 2 Part Number M378B5173BH0-CH9/K0/MA M378B1G73BH0-CF8/H9/K0/MA M391B1G73BH0-CF8/H9/K0/MA NOTE : 1. "##" - F8/H9/K0/ 1066Mbps 7-7- 1333Mbps 9-9 1600Mbps 11-11- 1866Mbps 13-13-13 - DDR3-1866(13-13-13) is backward compatible to DDR3-1600(11-11-11), DDR3-1333(9-9-9), DDR3-1066(7-7-7) - DDR3-1600(11-11-11) is backward compatible to DDR3-1333(9-9-9), DDR3-1066(7-7-7) - DDR3-1333(9-9-9) is backward compatible to DDR3-1066(7-7-7) 2. Key Features DDR3-800 Speed 6-6-6 tCK(min) 2.5 CAS Latency ...
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Unbuffered DIMM 4. x64 DIMM Pin Configurations (Front side/Back side) Pin Front Pin Back 121 REFDQ 122 DQ4 SS 3 DQ0 123 DQ5 V 4 DQ1 124 125 DM0 SS 6 ...
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Unbuffered DIMM 5. x72 DIMM Pin Configurations (Front side/Back side) Pin Front Pin Back 121 REFDQ 122 DQ4 SS 3 DQ0 123 DQ5 V 4 DQ1 124 125 DM0 SS 6 ...
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... NOTE : 1. Raw Cards D (1Rx8 ECC) and E (2Rx8 ECC) support a thermal sensor. 2. When the SPD and the thermal sensor are placed on the module placed but R2 is not. When only the SPD is placed on the module placed but R1 is not. [ Table 1 ] Temperature Sensor Characteristics ...
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... DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches DM0-DM8 the DQ and DQS loading. Power and ground for DDR3 SDRAM input buffers, and core logic Supply DD SS these modules. 1 DQS0-DQS8 SSTL Data strobe for input and output data. 1 DQS0-DQS8 These signals and tied at the system planar to either V SA0-SA2 - range ...
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... There is a via grid located under the DRAMs for wiring the CA signals (address, bank address, command, and control lines) to the DRAM pins. The length of the traces from the vias to the DRAMs places limitations on the bandwidth of the module. The shorter these traces, the higher the bandwidth. To extend the bandwidth of the CA bus for DDR3 modules, a scheme was defined to reduce the length of these traces ...
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... Unbuffered DIMM 9. Function Block Diagram: 9.1 4GB, 512Mx64 Non ECC Module (Populated as 1 rank of x8 DDR3 SDRAMs) S0 DQS0 DQS0 DM0 DM CS DQS DQS DQ0 I/O 0 DQ1 I DQ2 I/O 2 DQ3 I/O 3 DQ4 I/O 4 DQ5 I/O 5 DQ6 I/O 6 DQ7 I/O 7 DQS1 DQS1 DM1 DM CS DQS DQS DQ8 I/O 0 DQ9 I DQ10 ...
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... Unbuffered DIMM 9.2 8GB, 1Gx64 Non ECC Module (Populated as 2 ranks of x8 DDR3 SDRAMs DQS0 DQS0 DM0 DM CS DQS DQS DQ0 I/O 0 DQ1 I DQ2 I/O 2 DQ3 I/O 3 DQ4 I/O 4 DQ5 I/O 5 DQ6 I/O 6 DQ7 I/O 7 DQS1 DQS1 DM1 DM CS DQS DQS DQ8 I/O 0 DQ9 I DQ10 I/O 2 DQ11 I/O 3 DQ12 ...
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... Unbuffered DIMM 9.3 8GB, 1Gx72 ECC Module (Populated as 2 ranks of x8 DDR3 SDRAMs DQS0 DQS0 DM0 DM CS DQS DQS DQ0 I/O 0 DQ1 I DQ2 I/O 2 DQ3 I/O 3 DQ4 I/O 4 DQ5 I/O 5 DQ6 I/O 6 DQ7 I/O 7 DQS1 DQS1 DM1 DM CS DQS DQS DQ8 I/O 0 DQ9 I DQ10 I/O 2 DQ11 I/O 3 DQ12 I/O 4 DQ13 ...
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Unbuffered DIMM 10. Absolute Maximum Ratings 10.1 Absolute Maximum DC Ratings Symbol Parameter V Voltage on V pin relative Voltage on V pin relative to V DDQ DDQ V V Voltage on any pin relative ...
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Unbuffered DIMM 12. AC & DC Input Measurement Levels 12.1 AC & DC Logic Input Levels for Single-ended Signals [ Table 2 ] Single-ended AC & DC input levels for Command and Address Symbol Parameter V (DC100) DC input logic ...
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Unbuffered DIMM 12.2 V Tolerances. REF The dc-tolerance limits and ac-noise limits for the reference voltages function of time. (V stands for V REF REF V (DC) is the linear average of V (t) over ...
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Unbuffered DIMM 12.3 AC and DC Logic Input Levels for Differential Signals 12.3.1 Differential Signals Definition V .DIFF.AC.MIN .DIFF.AC.MAX IL Figure 3. Definition of differential ac-swing and "time above ac level" tDVAC 12.3.2 Differential Swing Requirement for ...
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Unbuffered DIMM 12.3.3 Single-ended Requirements for Differential Signals Each individual component of a differential signal (CK, DQS, CK, DQS) has also to comply with certain requirements for single-ended signals. CK and CK have to approximately reach V SEH half-cycle. DQS, ...
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Unbuffered DIMM 12.3.4 Differential Input Cross Point Voltage To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (CK, CK and DQS, DQS) ...
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Unbuffered DIMM 13. AC & DC Output Measurement Levels 13.1 Single Ended AC and DC Output Levels [ Table 8 ] Single Ended AC and DC output levels Symbol Parameter V (DC) DC output high measurement level (for IV curve ...
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Unbuffered DIMM 13.4 Differential Output Slew Rate With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between V (AC) for differential signals as shown in below. diff [ Table 12 ...
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Unbuffered DIMM 14. DIMM IDD specification definition Symbol Operating One Bank Active-Precharge Current CKE: High; External clock: On; tCK, nRC, nRAS, CL: Refer to Component Datasheet for detail pattern ; BL: 8 IDD0 Command, Address, Bank Address Inputs: partially toggling ...
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... Refer to DRAM supplier data sheet and/or DIMM SPD to determine if optional features or requirements are supported by DDR3 SDRAM device 7) IDD current measure method and detail patterns are described on DDR3 component datasheet 8) VDD and VDDQ are merged on module PCB. 9) DIMM IDD SPEC is measured with Qoff condition ...
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... IDD2Q 160 IDD3P 160 IDD3N 240 IDD4R 680 IDD4W 720 IDD5B 1160 IDD6 120 IDD7 1360 IDD8 120 M378B1G73BH0 : 8GB(1Gx64) Module CF8 Symbol (DDR3-1066@CL=7) IDD0 480 IDD1 560 IDD2P0(slow exit) 240 IDD2P1(fast exit) 240 IDD2N 320 IDD2Q 320 IDD3P 320 IDD3N ...
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... Unbuffered DIMM M391B1G73BH0 : 8GB(1Gx72) Module CF8 Symbol (DDR3-1066@CL=7) IDD0 540 IDD1 630 IDD2P0(slow exit) 270 IDD2P1(fast exit) 270 IDD2N 360 IDD2Q 360 IDD3P 360 IDD3N 450 IDD4R 810 IDD4W 855 IDD5B 1260 IDD6 270 IDD7 1350 IDD8 270 NOTE : 1. DIMM IDD SPEC is calculated with considering de-actived rank(IDLE) is IDD2N. ...
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... DM, DQS, DQS, TDQS, TDQS) Input/output capacitance of ZQ pin NOTE : This parameter is Component Input/Output Capacitance so that is different from Module level Capacitance. 1. Although the DM, TDQS and TDQS pins have different functions, the loading matches DQ and DQS 2. This parameter is not subject to production test verified by design and characterization. ...
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Unbuffered DIMM 17. Electrical Characteristics and AC timing (0 °C<T ≤95 ° 1.5V ± 0.075V; V CASE DDQ 17.1 Refresh Parameters by Device Density Parameter All Bank Refresh to active/refresh cmd time Average periodic refresh interval NOTE : ...
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Unbuffered DIMM [ Table 16 ] DDR3-1066 Speed Bins Speed CL-nRCD-nRP Parameter Internal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command ...
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Unbuffered DIMM [ Table 18 ] DDR3-1600 Speed Bins Speed CL-nRCD-nRP Parameter Intermal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command ...
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Unbuffered DIMM [ Table 19 ] DDR3-1866 Speed Bins Speed CL-nRCD-nRP Parameter Internal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command ...
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Unbuffered DIMM 17.3.1 Speed Bin Table Notes Absolute Specification ( 1.5V +/- 0.075 V); OPER DDQ DD NOTE : 1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a ...
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Unbuffered DIMM 18. Timing Parameters by Speed Grade [ Table 20 ] Timing Parameters by Speed Bins for DDR3-800 to DDR3-1333 (Cont.) Speed Parameter Clock Timing Minimum Clock Cycle Time (DLL off mode) Average Clock Period Clock Period Average high ...
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Unbuffered DIMM [ Table 20 ] Timing Parameters by Speed Bins for DDR3-800 to DDR3-1333 (Cont.) Speed Parameter Command and Address Timing DLL locking time internal READ Command to PRECHARGE Command delay Delay from start of internal write transaction to ...
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Unbuffered DIMM [ Table 20 ] Timing Parameters by Speed Bins for DDR3-800 to DDR3-1333 Speed Parameter Power Down Timing Exit Power Down with DLL on to any valid command;Exit Pre- charge Power Down with DLL frozen to commands not ...
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Unbuffered DIMM [ Table 21 ] Timing Parameters by Speed Bins for DDR3-1600, DDR3-1866 (Cont.) Speed Parameter Clock Timing Minimum Clock Cycle Time (DLL off mode) Average Clock Period Clock Period Average high pulse width Average low pulse width Clock ...
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Unbuffered DIMM [ Table 21 ] Timing Parameters by Speed Bins for DDR3-1600, DDR3-1866 (Cont.) Speed Parameter Command and Address Timing DLL locking time internal READ Command to PRECHARGE Command delay Delay from start of internal write transaction to internal ...
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Unbuffered DIMM [ Table 21 ] Timing Parameters by Speed Bins for DDR3-1600, DDR3-1866 Speed Parameter Power Down Timing Exit Power Down with DLL on to any valid command;Exit Pre- charge Power Down with DLL frozen to commands not requiring ...
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Unbuffered DIMM 18.1 Jitter Notes Specific Note a Unit ’tCK(avg)’ represents the actual tCK(avg) of the input clock under operation. Unit ’nCK’ represents one clock cycle of the input clock, counting the actual clock edges.ex) tMRD = 4 [nCK] means; ...
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Unbuffered DIMM 18.2 Timing Parameter Notes 1. Actual value dependant upon measurement level definitions which are TBD. 2. Commands requiring a locked DLL are: READ (and RAP) and synchronous ODT commands. 3. The max values are system dependent ...
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... Unbuffered DIMM 19. Physical Dimensions 19.1 512Mbx8 based 512M x64 Module (1 Rank) - M378B5173BH0 (2) 2.50 54.675 A 47.00 5.00 1.50±0.10 2.50 Detail A The used device is 512M x8 DDR3 SDRAM, FBGA. DDR3 SDRAM Part NO : K4B4G0846B-HC∗∗ * NOTE : Tolerances on all dimensions ±0.15 unless otherwise specified. datasheet 133.35 ± 0.15 128.95 N/A (for x64) ...
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... Unbuffered DIMM 19.2 512Mbx8 based 1Gx64/x72 Module (2 Ranks) - M378/91B1G73BH0 (2) 2.50 54.675 A 47.00 5.00 1.50±0.10 2.50 Detail A The used device is 512M x8 DDR3 SDRAM, FBGA. DDR3 SDRAM Part NO : K4B4G0846B-HC∗∗ * NOTE : Tolerances on all dimensions ±0.15 unless otherwise specified. datasheet 133.35 ± 0.15 128.95 N/A (for x64) SPD ECC (for x72 ...