M391B1G73BH0 SAMSUNG [Samsung semiconductor], M391B1G73BH0 Datasheet - Page 34

• Manufacturer Part Number: M391B1G73BH0
• Description: 240pin Unbuffered DIMM based on 4Gb B-die
• Manufacturer: SAMSUNG [Samsung semiconductor]

Unbuffered DIMM
[ Table 21 ] Timing Parameters by Speed Bins for DDR3-1600, DDR3-1866 (Cont.)
Clock Timing
Minimum Clock Cycle Time (DLL off mode)
Average Clock Period
Clock Period
Average high pulse width
Average low pulse width
Clock Period Jitter
Clock Period Jitter during DLL locking period
Cycle to Cycle Period Jitter
Cycle to Cycle Period Jitter during DLL locking period
Cumulative error across 2 cycles
Cumulative error across 3 cycles
Cumulative error across 4 cycles
Cumulative error across 5 cycles
Cumulative error across 6 cycles
Cumulative error across 7 cycles
Cumulative error across 8 cycles
Cumulative error across 9 cycles
Cumulative error across 10 cycles
Cumulative error across 11 cycles
Cumulative error across 12 cycles
Cumulative error across n = 13, 14 ... 49, 50 cycles
Absolute clock HIGH pulse width
Absolute clock Low pulse width
Data Timing
DQS,DQS to DQ skew, per group, per access
DQ output hold time from DQS, DQS
DQ low-impedance time from CK, CK
DQ high-impedance time from CK, CK
Data setup time to DQS, DQS referenced to V
els
Data hold time to DQS, DQS referenced to V
DQ and DM Input pulse width for each input
Data Strobe Timing
DQS, DQS differential READ Preamble
DQS, DQS differential READ Postamble
DQS, DQS differential output high time
DQS, DQS differential output low time
DQS, DQS differential WRITE Preamble
DQS, DQS differential WRITE Postamble
DQS, DQS rising edge output access time from rising CK, CK
DQS, DQS low-impedance time (Referenced from RL-1)
DQS, DQS high-impedance time (Referenced from RL+BL/2)
DQS, DQS differential input low pulse width
DQS, DQS differential input high pulse width
DQS, DQS rising edge to CK, CK rising edge
DQS,DQS falling edge setup time to CK, CK rising edge
DQS,DQS falling edge hold time to CK, CK rising edge
Parameter
Speed
IH
IH
(DC)V
(AC)V
IL
(DC) levels
IL
(AC) lev-
tCK(DLL_OFF)
tJIT(per, lck)
tERR(10per)
tERR(11per)
tERR(12per)
tJIT(cc, lck)
tERR(2per)
tERR(3per)
tERR(4per)
tERR(5per)
tERR(6per)
tERR(7per)
tERR(8per)
tERR(9per)
tERR(nper)
tDS(base)
tDS(base)
tDH(base)
tHZ(DQS)
tLZ(DQS)
tCK(avg)
tCK(abs)
tCH(avg)
tCL(avg)
tCH(abs)
tCL(abs)
tDQSCK
Symbol
tJIT(per)
tLZ(DQ)
tHZ(DQ)
tJIT(cc)
tDQSQ
tWPRE
tWPST
tDQSH
AC150
AC135
DC100
tRPRE
tRPST
tDQSL
tDQSS
tDIPW
tQSH
tDSS
tDSH
tQSL
tQH
datasheet
tCK(avg)min + tJIT(per)min
-0.27
0.47
0.47
-103
-122
-136
-147
-155
-163
-169
-175
-180
-184
-188
0.43
0.43
0.38
-450
-225
-450
0.45
0.45
0.18
0.18
MIN
360
-70
-60
0.9
0.3
0.4
0.4
0.9
0.3
10
45
8
-
-
-
-
DDR3-1600
- 34 -
140
120
tERR(nper)max = (1 + 0.68ln(n))*tJIT(per)max
tERR(nper)min = (1 + 0.68ln(n))*tJIT(per)min
tCK(avg)max +
tJIT(per)max
NOTE 19
NOTE 11
MAX
0.53
0.53
0.55
0.55
0.27
103
122
136
147
155
163
169
175
180
184
188
100
225
225
225
225
225
70
60
-
-
-
-
-
-
-
-
-
-
-
-
-
-
See Speed Bins Table
tCK(avg)min +
tJIT(per)min
-0.27
0.47
0.47
-105
-117
-126
-133
-139
-145
-150
-154
-158
-161
0.43
0.43
0.38
-390
-195
-390
0.45
0.45
0.18
0.18
MIN
320
-60
-50
-88
0.9
0.3
0.4
0.4
0.9
0.3
20
8
0
-
-
-
-
DDR3-1866
120
100
tCK(avg)max +
tJIT(per)max
NOTE 19
NOTE 11
DDR3 SDRAM
MAX
0.53
0.53
0.55
0.55
0.27
105
117
126
133
139
145
150
154
158
161
195
195
195
195
195
60
50
88
85
-
-
-
-
-
-
-
-
-
-
-
-
-
-
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
Units
ns
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
Rev. 1.3
13, 19, g
11, 13, b
12,13,14
13,14, f
13,14, f
13,14,f
NOTE
29, 31
30, 31
13, g
d, 17
d, 17
d, 17
13, g
13, g
c, 32
c, 32
13,f
24
25
26
13
28
6
c