M391B5273CH0 SAMSUNG [Samsung semiconductor], M391B5273CH0 Datasheet - Page 33

• Manufacturer Part Number: M391B5273CH0
• Description: 240pin Unbuffered DIMM based on 2Gb C-die
• Manufacturer: SAMSUNG [Samsung semiconductor]

Unbuffered DIMM
[ Table 19 ] Timing Parameters by Speed Bin (Cont.)
Power Down Timing
Exit Power Down with DLL on to any valid com-
mand;Exit Precharge Power Down with DLL
frozen to commands not requiring a locked DLL
Exit Precharge Power Down with DLL frozen to com-
mands requiring a locked DLL
CKE minimum pulse width
Command pass disable delay
Power Down Entry to Exit Timing
Timing of ACT command to Power Down entry
Timing of PRE command to Power Down entry
Timing of RD/RDA command to Power Down entry
Timing of WR command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
Timing of WRA command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
Timing of WR command to Power Down entry
(BC4MRS)
Timing of WRA command to Power Down entry
(BC4MRS)
Timing of REF command to Power Down entry
Timing of MRS command to Power Down entry
ODT high time without write command or with write
command and BC4
ODT high time with Write command and BL8
Asynchronous RTT turn-on delay (Power-Down with
DLL frozen)
Asynchronous RTT turn-off delay (Power-Down with
DLL frozen)
RTT turn-on
RTT_NOM and RTT_WR turn-off time from ODTLoff
reference
RTT dynamic change skew
First DQS pulse rising edge after tDQSS margining
mode is programmed
DQS/DQS delay after tDQS margining mode is pro-
grammed
Write leveling setup time from rising CK, CK crossing to
rising DQS, DQS crossing
Write leveling hold time from rising DQS, DQS crossing
to rising CK, CK crossing
Write leveling output delay
Write leveling output error
ODT Timing
Write Leveling Timing
Parameter
Speed
tWRAPDEN
tWRAPDEN
tMRSPDEN
tWLDQSEN
tACTPDEN
tREFPDEN
tWRPDEN
tWRPDEN
tPRPDEN
tRDPDEN
tWLMRD
tCPDED
tAONPD
tAOFPD
Symbol
tXPDLL
ODTH4
ODTH8
tWLOE
tWLH
tWLO
tCKE
tAON
tAOF
tADC
tWLS
tXP
tPD
WL +2 +WR
tMOD(min)
tCKE(min)
RL + 4 +1
tCK(avg))
tCK(avg))
(10nCK,
+WR +1
(3nCK,
(3nCK,
WL + 4
+(tWR/
WL + 4
WL + 2
+(tWR/
7.5ns)
7.5ns)
24ns)
MIN
max
max
max
-400
325
325
0.3
0.3
+1
40
25
datasheet
1
1
1
1
4
6
2
2
0
0
DDR3-800
9*tREFI
MAX
400
8.5
8.5
0.7
0.7
9
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
WL +2 +WR
tMOD(min)
tCKE(min)
- 33 -
RL + 4 +1
tCK(avg))
tCK(avg))
5.625ns)
(10nCK,
+WR +1
WL + 4
WL + 4
WL + 2
(3nCK,
(3nCK,
+(tWR/
+(tWR/
7.5ns)
24ns)
-300
MIN
max
max
max
245
245
0.3
0.3
+1
40
25
1
1
1
1
4
6
2
2
0
0
DDR3-1066
9*tREFI
MAX
300
8.5
8.5
0.7
0.7
9
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
WL + 4 +WR
WL +2 +WR
(3nCK,6ns)
tMOD(min)
tCKE(min)
RL + 4 +1
tCK(avg))
tCK(avg))
5.625ns)
(10nCK,
WL + 4
WL + 2
(3nCK,
+(tWR/
+(tWR/
24ns)
-250
MIN
max
max
max
195
195
0.3
0.3
+1
+1
40
25
1
1
1
1
4
6
2
2
0
0
DDR3-1333
9*tREFI
MAX
250
8.5
8.5
0.7
0.7
9
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
WL + 4 +WR
WL +2 +WR
(3nCK,6ns)
(3nCK,5ns)
tMOD(min)
tCKE(min)
RL + 4 +1
tCK(avg))
tCK(avg))
(10nCK,
WL + 4
WL + 2
+(tWR/
+(tWR/
24ns)
-225
MIN
max
max
max
165
165
0.3
0.3
+1
+1
40
25
1
1
1
1
4
6
2
2
0
0
DDR3-1600
DDR3 SDRAM
9*tREFI
MAX
225
8.5
8.5
0.7
0.7
7.5
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
tCK(avg
tCK(avg
Units
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
tCK
tCK
tCK
ns
ns
ps
ps
ps
ns
ns
)
)
Rev. 1.21
NOTE
20,21
15
20
20
10
10
7,f
8,f
2
9
9
3
3
f