M391B5273CH0 SAMSUNG [Samsung semiconductor], M391B5273CH0 Datasheet - Page 8

• Manufacturer Part Number: M391B5273CH0
• Description: 240pin Unbuffered DIMM based on 2Gb C-die
• Manufacturer: SAMSUNG [Samsung semiconductor]

Unbuffered DIMM
8. Input/Output Functional Description
NOTE :
1. DM8, DQS8 and DQS8 are for ECC UDIMM only.
CK0-CK1
CK0-CK1
CKE0-CKE1
S0-S1
ODT0-ODT1
V
V
V
BA0-BA2
A0-A14
DQ0-DQ63
CB0-CB7
DM0-DM8
V
DQS0-DQS8
DQS0-DQS8
SA0-SA2
SDA
SCL
V
RESET
EVENT
RAS, CAS, WE
REFDQ
REFCA
DDQ
DD
DDSPD
,V
Symbol
SS
1
1
1
Supply
Supply
Supply
Supply
Supply
Output
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Type
-
-
-
-
CK and CK are differential clock inputs. All the DDR3 SDRAM addr/cntl inputs are sampled on the crossing of positive
edge of CK and negative edge of CK. Output (read) data is reference to the crossing of CK and CK (Both directions of
crossing)
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low
initiates the Power Down mode, or the Self-Refresh mode
Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the
command decoder is disabled, new command are ignored but previous operations continue. This signal provides for
external rank selection on systems with multiple ranks.
RAS, CAS, and WE (ALONG WITH S) define the command being entered.
When high, termination resistance is enabled for all DQ, DQS, DQS and DM pins, assuming the function is enabled in the
Extended Mode Register Set (EMRS).
Reference voltage for SSTL 15 I/O inputs.
Reference voltage for SSTL 15 command/address inputs.
Power supply for the DDR3 SDRAM output buffers to provide improved noise immunity. For all current DDR3 unbuffered
DIMM designs, V
Selects which SDRAM bank of eight is activated.
During a Bank Activate command cycle, Address input defines the row address (RA0-RA13)
During a Read or Write command cycle, Address input defines the column address, In addition to the column address,
AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is
selected and BA0, BA1, BA2 defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a pre-
charge command cycle, AP is used in conjunction with BA0, BA1, BA2 to control which bank(s) to precharge. If AP is
high, all banks will be precharged regardless of the state of BA0, BA1 or BA2. If AP is low, BA0, BA1 and BA2 are used
to define which bank to precharge. A12(BC) is sampled during READ and WRITE commands to determine if burst chop
(on-the-fly) will be performed (HIGH, no burst chop; Low, burst chopped).
Data and Check Bit Input/Output pins.
DM is an input mask signal for write data. Input data is masked when DM is sampled High coincident with that input data
during a write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches
the DQ and DQS loading.
Power and ground for DDR3 SDRAM input buffers, and core logic. V
these modules.
Data strobe for input and output data.
These signals and tied at the system planar to either V
range.
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. An external resistor may be connected
from the SDA bus line to V
This signal is used to clock data into and out of the SPD EEPROM. An external resistor may be connected from the SCL
bus time to V
Power supply for SPD EEPROM. This supply is separate from the V
from 3.0V to 3.6V.
The RESET pin is connected to the RESET pin on each DRAM. When low, all DRAMs are set to a know state.
This signal indicates that a thermal event has been detected in the thermal sensing device. The system should guarantee
the electrical level requirement is met for the EVENT pin on TS/SPD part
DDSPD
DDQ
to act as a pull-up on the system board.
shares the same power plane as V
DDSPD
datasheet
to act as a pull-up on the system board.
- 8 -
SS
Function
DD
or V
pins.
DDSPD
DD
DD
to configure the serial SPD EERPOM address
/V
and V
DDQ
power plane. EEPROM supply is operable
DDQ
pins are tied to V
DDR3 SDRAM
DD
/V
DDQ
Rev. 1.21
planes on