HYS64D64020GBDL-6-C INFINEON [Infineon Technologies AG], HYS64D64020GBDL-6-C Datasheet - Page 20

• Manufacturer Part Number: HYS64D64020GBDL-6-C
• Description: 200-Pin Small Outline Dual-In-Line Memory Modules
• Manufacturer: INFINEON [Infineon Technologies AG]

Table 13
Parameter
Read preamble
Read postamble
Active to Precharge command
Active to Active/Auto-refresh command period
Auto-refresh to Active/Auto-refresh command
period
Active to Read or Write delay
Precharge command period
Active to Autoprecharge delay
Active bank A to Active bank B command
Write recovery time
Auto precharge write recovery + precharge
time
Internal write to read command delay
Exit self-refresh to non-read command
Exit self-refresh to read command
Average Periodic Refresh Interval
1) 0 C
2) Input slew rate
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
4) Inputs are not recognized as valid until
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
7)
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
10) Fast slew rate
11) For each of the terms, if not already an integer, round to the next highest integer.
12) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Data Sheet
(DDR400)
level for signals other than CK/CK, is
t
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on
system performance (bus turnaround) degrades accordingly.
ns, measured between
cycle time.
HZ
and
T
t
A
LZ
AC Timing - Absolute Specifications for PC3200 and PC2700
transitions occur in the same access time windows as valid data transitions. These parameters are not referred
70 C
1.0 V/ns , slow slew rate
1 V/ns for DDR400, DDR333
; V
DDQ
V
IH(ac)
= 2.5 V
and
V
0.2 V,
IL(ac)
V
REF
V
REF
.
V
. CK/CK slew rate are
0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/
DD
stabilizes.
= +2.5 V
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
RPRE
RPST
RAS
RC
RFC
RCD
RP
RAP
RRD
WR
DAL
WTR
XSNR
XSRD
REFI
20
0.2 V (DDR333);
Min.
0.9
0.40
40
55
70
15
15
t
10
15
(
2
75
200
—
RCD
t
WR
DDR400B
/
t
or
CK
1.0 V/ns.
–5
t
Small Outline DDR SDRAM Modules
)+(
RASmin
Max.
1.1
0.60
70E+3
—
—
—
—
—
—
—
—
—
7.8
t
RP
HYS64D64020[H/G]BDL–[5/6]–C
/
V
t
CK
DDQ
)
Min.
0.9
0.40
42
60
72
18
18
12
15
1
75
200
—
t
= 2.6 V
CK
DDR333
is equal to the actual system clock
–6
Max.
1.1
0.60
70E+3 ns
—
—
—
—
—
—
—
—
—
7.8
t
DQSS
Electrical Characteristics
0.1 V,
.
Unit Note/ Test
t
t
ns
ns
ns
ns
ns
ns
ns
t
t
ns
t
CK
CK
CK
CK
CK
V
s
DD
Rev. 1.1, 2004-05
= +2.6 V
Condition
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)11)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)12)
0.1 V
V
1)
TT
.